Conflicting register addresses in RFSoC OFDM

Support
1

Hi @Axdy , I’m working on a custom RFSoC board. I’ve been trying to validate OFDM. In the source code , in ofdm.py file, I have noticed that in the OFDMRxCore class, decorator for receive_enable were not proper. Also receive_enable and reset register address were same on source code. Could you please check on this.

class OFDMRxCore(DefaultIP):

def _init_(self,description):
super()._init_(description=description)

bindto = [“xilinx.com:ip:ofdm_rx:0.4”]

@property
def reset(self):
return self.read(0x0)

@reset.setter
def reset(self, reset):
self.write(0x0, reset)

@property
def receive_enable(self):
return self.read(0x0)

@reset.setter # Issue decorator
def receive_enable(self, enable):
self.write(0x0, enable)

2

Hi @vrb,

This seems like a copy paste mistake. It should be

@reset.receive_enable
def receive_enable(self, enable):
    self.write(0x0, enable)

I suggest you PR the changes.

Mario