Could not find IP or hierarchy in overlay

PYNQ VERSION: pynq V2.0 image
Board Name: PYNQ Z1

I created a block design for my Verilog RTL and generated the bitstream too. When I added the bitstream file in jupyter notebook, I got an error like “Could not find IP or hierarchy in Overlay”.

The above image is my block design and I will attach the error I got in Jupyter notebook. Please help me, my whole project depends on this.

Hi @Arun_Kumar_Kurapati,

I’m not sure that you are using the correct name for your hierarchy it looks like in the block diagram your hierarchy is called new_hier but in the notebook you’re referring it to as newpd_hier.

In the notebook you can double check all the names of the hierarchy in the design by typing overlay.hierarchy_dict.

Hope that helps!

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