I created a block design for my Verilog RTL and generated the bitstream too. When I added the bitstream file in jupyter notebook, I got an error like “Could not find IP or hierarchy in Overlay”.
I’m not sure that you are using the correct name for your hierarchy it looks like in the block diagram your hierarchy is called new_hier but in the notebook you’re referring it to as newpd_hier.
In the notebook you can double check all the names of the hierarchy in the design by typing overlay.hierarchy_dict.
