Hi everyone,
This is the first time I use PYNQ-Z1 board. After getting the Reed-Solomon_Encoder IP from Xilinx and generating the Bitstream, I tried to upload it on my PYNQ-Z1 board but i received this error:
“Could not find IP or hierarchy axi_dma_0 in overlay”
PS: I’m pretty sure that I already inserted a DMA and connected it with the other components.
You can run the following to show details of the IP in your system:
rs.design.hierarchy_dict
You may just have a name mismatch.
Cathal
Hi Cathal,
thank you for your response. I did what you suggested but I got this (I made a new Python file and I chnaged rs_design by test_design but I did the same instructions)
Which version of PYNQ are you using?
I just noticed that you are not including the HWH with your .bit. Can you add that?
Can you post your block diagram?
Cathal
I created my Vivado project using the PYNQ ZYNQ board part “xc7z020clg400-1” (because I have a PYNQ-Z1 board).
I did include the .hwh file with my .bit file. (I uploaded it in my jupyter folder where I created my python file)
@Oumayma can you report the output of
for i in test_design.ip_dict:
print(i)
Can you also rename/delete design_1_wrapper.tcl? to make sure pynq is reading from *.hwh
Mario
Hey @marioruiz, so I did some changes and I tried the instruction you gave me and this is the output.
Now it can find the DMA but still can’t find the Reed-Solomon encoder.
Hi @Oumayma, you will not find the rs_encoder IP because it does not have an AXI4 memory mapped interface.
However, you should be able to start transferring data through DMA and get the result. Provided the IP works.
Mario
Hi @marioruiz I tried to transfer data through the DMA like mentioned in the figure below.
At first, when I ran the function “run_kernel()”, it took more than 10 min and it didn’t finish running so I tried to reload the page but now when I run the function “run_kernel()” I get this error:
RuntimeError Traceback (most recent call last)
in ()
----> 1 run_kernel()
in run_kernel()
1 def run_kernel():
----> 2 dma.sendchannel.transfer(inbuf)
3 dma.recvchannel.transfer(outbuf)
4 dma.sendchannel.wait()
5 dma.recvchannel.wait()
/usr/local/lib/python3.6/dist-packages/pynq/lib/dma.py in transfer(self, array)
120 raise RuntimeError(‘DMA channel not started’)
121 if not self.idle and not self._first_transfer:
→ 122 raise RuntimeError(‘DMA channel not idle’)
123 if self._flush_before:
124 array.flush()
RuntimeError: DMA channel not idle
Is you IP setting tlast when the compute ends? The DMA expects a tlast to finish moving data.
I suggest to include an ILA in the design to check if the output is correct.
@marioruiz could you please explain more?
I’m new in this filed and my whole project relies on this.
How can I implement the TLAST and the ILA?
@marioruiz was asking about TLAST. The DMA needs that signal to be part of the M_AXIS_OUTPUT channel.
If you go back and check, I think you should find a warning somewhere to say this is disconnected. If you have a lot of warning messages in Vivado it can be tedious to check them all, but it can be worth doing this if you have a problem.
I think this is included by default (you can check by expanding the M_AXIS_OUTPUT port):
What configuration setting did you use for the IP, if any?
If you double click this IP you can configure it. I notice that m_axis_output_tready doesn’t seem to be enabled by default. This would prevent the IP from working with the DMA and causing the hang you see.
I’d suggest you check this, enable it if necessary, rebuild the design and test it again.
Cathal
Hi @cathalmccabe,
I tried to follow your instructions you and @marioruiz , so I inserted the ILA system and configured my Reed Solomon IP to have the m_axis_output_tlast and connected it to my DMA.
When I validate the design I get this warning:
Hi @Oumayma,
The input and output stream in the IP are 8-bit wide, however the DMA output is 32-bit wide. This is the meaning of the warning you are seeing. You need to modify the DMA to match the data width of the IP.
Mario
@marioruiz, I modified my DMA like you told me and the warning is gone.
However, I still have the same problem in jupyter notebook.
It took more than 30 min running and didn’t finish till now.
I don’t know what’s wrong with it.
You need to make sure that you are feeding enough data to the IP and the output buffer is big enough to receive the result.
Please verify the IP documentation,
https://www.xilinx.com/support/documentation/ip_documentation/rs_encoder/v9_0/pg025_rs_encoder.pdf
I also suggest to run the IP test bench to understand better how it works.
Mario
I have the same problem as him, I can’t find the IP in jupyter. But I didn’t get an error when I used system ILA design valid, so what was wrong with me?
Please post this as a new question.
Cathal
