I have validated my design in HLS and i have exported the ip. I am trying to create a block design and i am facing an issue. I have one dma controller for accessing the axis port of one of the input. I want to know how can i integrate the remaining input interfaces? should i create an individual dma block for all of them?
design_1.pdf (78.2 KB)
I don’t understand the question, you mean the outputs of your DMA? One thing that I am seeing wrong is that you need to connect the DMA to ZYNQ with a HPO port like this:
Once you enable the HPO port, vivado will tell you to automatic connect, and will create also the axi_smc
Thanks my doubt is how to create the block connection system for my custom hls ip which has streaming inputs and outputs. Should i connect the dma to the processor using axismart connect?
once you enable the HPO port in the ZYNQ, vivado will tell you to run automotion, click on it and will connect the DMA to the ZYNQ through the axismart connect, so there is no need to add it mannualy.
I see that you have 2 inputs of stream buffer. Maybe you can just do It with one DMA modifying the bus length, I’ve never needed 2 DMA, but you can try it, in this case you will need to enable another HPO port to the ZYNQ.
IN the SDK is easy working with the DMA, just send the buffer through the DMA address and read the result of it.
I attach you how I would do it.
My doImhProc IP has just one stream buffer input, that’s why M_AXIS_MM2S of axi_dma_1 is unconnected (in my case I don’t need 2 DMA, it’s just to show you how I would do it).
design_2.pdf (105.6 KB)
Another way to do this is to use AXI master interfaces in your HLS code instead of streams. The Master interfaces can read/write data directly to memory.
You would connect these interfaces to the Zynq HP ports.
See from page 114 here, and look at example on page 118:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug902-vivado-high-level-synthesis.pdf
Cathal
