Creating an AXI Stream IP that connects to DMA

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Hi, I am trying to use the AXI Stream to quickly transfer data to from PL to the PS, the architecture more or less looks like the one illustrated here: DMA — Python productivity for Zynq (Pynq).

I am trying to find tutorials but I cannot find one that teaches how to create the AXI Stream IP and connect it to the DMA,
this tutorial does: Developing Verilog AXI Stream Overlays and interfacing to ZYNQ, but it has many errors and it seems to not work.

Any tips would be appreciated!

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Hi Ying- I am guessing some of the Vivado stuff was updated and the tutorial is no longer valid. I will work on it this weekend and let you know.

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Hi Ying- I am working on GitHub - rogerpease/AXISlaveStreamTutorial … Also working on a MasterStream one but if you want to try this and feed back any comments would be appreciated.

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Will do, thank you much!

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Here’s the other one… GitHub - rogerpease/AXIMasterStreamTutorial

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Thank you!