Custom HLS IP block using DMA

  • I am using Vitis 2022.1, Vivado 2022.1 and Pynq v3.0 on Pynq-Z2.

I developed a custom HLS block following the tutorial on pp4fpga following this tutorial High_Level_Synthesis_for_FPGAs/Lab2 at main · ZongRuLi/High_Level_Synthesis_for_FPGAs · GitHub

I get all 0x00 results back from the DMA even when using the hardware from the original repo in the link.

Here is my design:
design_1_wrapper.bit (3.9 MB)
design_1_wrapper.hwh (317.4 KB)
DMA_TEST.ipynb (5.3 KB)

I cannot figure out what I am doing wrong, the implemented code (High_Level_Synthesis_for_FPGAs/streamMul.cpp at main · ZongRuLi/High_Level_Synthesis_for_FPGAs · GitHub ) is working fine in Simulation (HLS)

1 Like

I am not sure, but could you try adding tlast & tkeep signal to the hls code. It might solve your issue.

Hi Mizan,
thanks for your reply, I solved this issue myself (Python code problem in Jupyter Notebook)
solution in the attachment.
SingleDMA.ipynb (8.0 KB)