Multiple DMA: stall!

So I am following this guide, but it seems that using vivado 2022.1, when running validation it throws some errors about tlast and about the custom IP write channel byte size.

If you ignore the errors and compile anyway, then when using jupyter, there is a stall.

Has anyone else found that it is the case? Been stuck for a day! HELP!


Hi @alienflip,

Welcome to our community. As you are using the tools 2022.1, the HLS compiler is Vitis HLS not Vivado HLS.

Vitis HLS does not generate AXI4-Stream from structure properly. To generate AXI4-Stream interfaces you need to use something like this hls::stream< ap_axis<32,0,0,0>.

You can review Cathal’s tutorial for more information.


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If you take a closer look at his example link. It is using 2020.2 Vivado and Vitis HLS.
Meantime there do no tlast signal are generate accordingly.
So this lead to 2 major questions:
PYNQ 2.7 DMA according to the example can work without tlast signal?
Any major differences between DMA on PYNQ revisions?

The DMA could complete the transaction when the right amount of data is moved (still need to verify this claim) or when TLAST is asserted.

The DMA IP is from the Vivado IP Catalog, the PYNQ driver only configures it.


@briansune where do you see that the example can work without TLAST? OP mentions an stall, this is highly likely due to the fact that no TLAST is being generated.

Just from the capture of the blocks, maybe I am wrongly seen.
And the report of the HLS signals

I don’t think the example is fully verified, I can see a few inconsistencies. At the begging vivado_hls is called, but some of the screenshots are from vitis_hls

axis_t is a struct defined in the header file that is composed of an int data and an ap_uint<1> last. The 1-bit last is required for axis interfaces, and signals the last struct of the stream, ending the stream.

As I mentioned in my first reply, Vitis HLS does not support custom structs to generate AXI4-Streams



If this example really rely tlast to work why the interface of single and multiple DMA makes the same interface report.
Of cause this can be another clone example from other place but sure that if two examples following the same flow then it is really what it can do wo the tlast (I guess).

Whatever agree or disagree, I think we do agree one point is that it is a very bad design if this is relying on the enough amount of data passing to the DMA while using tlast only suffer really little LEs usage and introduce a much much complete handshaking protocol.

@briansune @marioruiz Thanks!

So for this guide and this guide, I guess we should be using vivado/vitis 2020.2?

Lastly: are there any up-to-date equivalents for 2022.1 that you guys know of?

I guess we should be using vivado/vitis 2020.2?

If you do not want to do any changes, yes.

I am not aware of any up to date version.

You should report this problem with them GitHub - KastnerRG/Read_the_docs: Projects and Labs for the Parallel Programming for FPGAs book