I recreate the base_overlay on vivado and delete what I don’t need for my project.
The problem I encountered after successfully loading the bitstream on the board
Below is the screenshot of the problem and the block design
I recreate the base_overlay on vivado and delete what I don’t need for my project.
The problem I encountered after successfully loading the bitstream on the board
Below is the screenshot of the problem and the block design
Hi @joshua20000216,
Welcome to the PYNQ community.
There’s a dedicated driver for the base overlay that configures some clocks.
Mario
So I need to load the ‘base.py’ on the board too?
btw, thank you for your quick reply.
I am the beginner on FPGA, this pynq stuff is my college project
I do my best for searching the imformation on internet, so if my question is stupid, I am sorry about that.
So I need to load the ‘base.py’ on the board too?
No, the configuration for those clocks will be erased when you download you custom overlay.
You need to configure the IP and clocks as the _init_clocks
function is doing.
Mario