PYNQ: PYTHON PRODUCTIVITY

DMA array transfer order

hdl.zip (10.1 KB)

Hi, i’m having trouble understanding data type representations and their transfers. I have followed this tutorial to create a custom IP with streaming interfaces. I did not use the files in Verilog, i followed the tutorial with VHDL with this Overlay as a result:

Parameters:

  • Zynq:
    S AXI HP0 DATA WIDTH: 64 – (With 32 is even worse, i get 400, 400, 600, 600 and then 0’s. Any idea why?)
  • DMA:
    Everything to 32 bits. Address width, memory map data width, stream data width. After all the tutorial uses 32 bit signals.

The problem i’m getting is testing the slave streaming interface from Pynq. I’m getting the values on a different order.

as you can see, i get 400, 500, 600 … and the last 4 values are 0. My guess is that by the time 700 arrives, TLAST is 1 and the Streaming state machine goes to IDLE. But the order of the streaming is correct, it is not 400, 500, 600, 700, 0, 100, 200, 300 as one can see debugging

The order is correct, and the TLAST is up when the whole array is done.

On the other hand, when i run the test for the master streaming interface:

it works smoothly, starting at 150 and streaming the next 8 words to the buffer.

Interestingly, here the streaming order is as in the previous case:

First the last 4 integers, then the first 4 integers. Even after TLAST was risen.

Any idea why this is so?
Any info or article on the subject will be appreciated.