I’m trying to test an HLS core that outputs a single 256 bit wide AXI stream (8 complex< ap_uint<16> >) that asserts TLAST ever 256 transactions (so 8kB). I’ve connected it to an AXI DMA’s S2MM port and I thought I’ve gotten all the various widths and settings right.
Over in my test notebook I’ve tried allocating an array of 2048 np.uint32 (so 8kB) and used that to kick off the transfer. I am getting data and things are mostly right, but I’m thinking they are shifted by 128bits and I might be seeing some other issues.
Presently I’m re-implementing with a System ILA to look more but for now I’m wondering if I’m even on the right track? Perhaps the issue is that I need to override the DMA receive channels length to specify 256 transactions instead of 8192, but I thought that length should be the number of bytes.