PYNQ: PYTHON PRODUCTIVITY

Zynq7000: Data loss in HP Stream from AXI DMA

Hi there,
I have a very strange problem with AXI DMA in all modes.
I have a custom AXIS IP generating packets of 255 bytes with TLAST. The IP connects to AXI DMA with the shown parameters (but I obtained the same problem in SG mode and for AXIS of 32 bits)

The DMA connects to HP0 slave of the Zynq 7000 processing system via AXI memory interconnect in the region 0x0000_0000 0x0000_FFFF.
All PL logic clocked by external clock of 125 MHz.
This IP works correctly in simulation, but when I use it on the board, I receive from the DMA only 128 bytes grouped by 4 with unexpected zeros, for example (buffer is organized by pairs of uint32 numbers):

PynqBuffer([[2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2863311530,          0],
            [2997529258,          0],
            [3675985473,          0],
            [1828241205,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0],
            [         0,          0]], dtype=uint32)

I really don’t understand why I lose data in the strange manner. I think that it can be memory problem because of the 32 bits losing, but I don’t really know.

Best regards.

Can you try the solution in Vector addition, correct output only on every other elements

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Thank you very much. It finally works.
Definitely, in Red Pitaya 125-14 one must use 64bit-wide HP ports.
It could be very useful for Zynq newbies like as me. :slight_smile:

2 Likes