Hi,
When I use DMA to transfer data, at first, it is ok. when I change to data, it has an error like this.
So I want to know how to align memory? When I define the address alignment using ‘allocate()’. Thank you! I have seen one answer to skip the alignment(modify in Vivado). But in my case, it is better to do the alignment.
That is a bug in the DMA driver - we’ve not tested widths that aren’t a power of 2 and in this case the alignment should be 4 or 8 not 6. All buffers from allocate will be at least page (i.e. 4096 byte) aligned. Would you be able to share your hwh file and we’ll come up with a workaround?
Peter
Thank you for reply. So, I will share.ZCU104_6_L15_SG_9pin_add_time_interpret_48ohm_unalign.hwh (369.2 KB)
Can you edit the pynq/lib/dma.py file on lines 710 and 727 from 6 to data_width. Looks like some refactoring introduced an error.
[Edit] Same with 652 and 669
Peter
It works. Thank you!
I created a pull request to rectify.
