RuntimeError:"DMA does not support unaligned transfers"

[nirsap]

Hi,
I got the following error on dma transaction.
I found similar issue in this forum but for my design it didn’t help.
I double clicked on the DMA block and checked the box allowing unaligned transfers.
Detailes" PYNQ v.3.0.1, Board ZCU208, jupyter notebook

RuntimeError:
dma.sendchannel.transfer(tx_buffer)
dma.sendchannel.wait()
File dma.py:154, in _SDMAChannel.transfer(self, array, start, nbytes)
148 raise RuntimeError(
149 "DMA does not support unaligned transfers; "
150 "Starting address must be aligned to "
151 “{} bytes.”.format(self._align)

DMA settings:

[briansune]

@nirsap

You need to post the DMA settings of the hardware block (Vivado Project) to allow modulator or others to help out.
Too few info to help out on this.

Bests

[nirsap]

Done
Thanks

[briansune]

@nirsap @marioruiz

I am not sure I read this correct.
From the Python script:
Are you trying to write to a DMA driver while it is disabled with WR?

Bests

[nirsap]

Hi,
The definition is correct, this DMA reads the data from the memory and transfer it to the next module at the axi stream port.
The Write channel is not used here.
Thanks

[briansune]

@nirsap

As you said DMA “READ” from data so are you suppose to use receive rather than transfer?
While DMA transfer it to next module aka next module received data from DMA aka DMA write to next module?

@marioruiz or @cathalmccabe could help better.

[nirsap]

Thanks for your help, I hope it will be more clear:
The DMA (axi_dma_tx) reads the DATA at the “Read Channel” (Using port M_AXI_MM2S) and transfer it to the next module (enc_hier) at AXI STREAM protocol using port M_AXIS_MM2S.
I have to mention that the design works fine and the transaction ended successfully (verified by chipscope) but it get stuck after the RuntimeError at the jupyter notebook.

[briansune]

@nirsap

Now this has become very confused:
Chipscope or System-ILA?
Why two DMAs signals are not aligned with the image you had post from beginning?
Transaction ended successfully aka signals are what states?

Let’s wait @cathalmccabe answer. They are better on these questions.

But I will highly suggest u look from most common FIR DMA example:

ZYNQ Ultrascale+ FIR DMA

Hello all, After the MNIST on ZYNQ example, it is time to move to a better and more powerful platform ZYNQ Ultrascale (ARM is more powerful). This FIR example is based on the previous example here. Although this is preformed on ZYNQ rather than ZYNQ-Ultrascale+, both platforms are so similar. In this example we are going to compare both software Python signal filter and HW accelerated filter. Lets start with the overall block-diagram. fir_acc.pdf (385.5 KB) [image] Take a closer lo…

[nirsap]

Thanks.
System-ILA.
I meant successfully by the meaning of the expected data at the M_AXI_S2MM port of axi_dma_tx_2.
The image at the beginning of the post is just for axi_dma_tx.
The right dma (axi_dma_tx_2) is settings are:

[briansune]

@nirsap

Well if you are sure u need unaligned transfer which the block in between alignment is not given:
According to this post:

RuntimeError: DMA does not support unaligned transfers; Starting address must be aligned to 6 bytes

I literally follow the DMA guide provided here: https://pynq.readthedocs.io/en/v2.6.1/pynq_libraries/dma.html#pynq-libraries-dma I suspect that I must do something to align the memory address?? But there is nothing in the documentation of Allocate that allows user to align memory: https://pynq.readthedocs.io/en/v2.6.1/pynq_libraries/allocate.html What should I do? Thanks for the help in advance. [image]

Please make sure the allocate is correctly.

[nirsap]

Hi,
I’m not sure that the problem is with the allocation.
I followed the guide
https://pynq.readthedocs.io/en/v2.6.1/pynq_libraries/allocate.html
The Solution for this issue didn’t help for me.

Solution from Feb’21: “Did you create your own overlay? I created my own with the DMA controller and I think I received the same error the first. I double clicked on the DMA block and checked the box allowing unaligned transfers and it worked for me. I hope this helps”

[briansune]

@nirsap

As you proposed, you do used System-ILA to debug.
While there are no debug capture here and the script body itself only show 1 line and no clue to know what is above and how the data is being transfer.

Meanwhile, you do mention design “works fine” and TX ended.
We can only use what info you provide to logically point out the possible issue.
Try use aligned transfer and zero padding to simply the behavior first.
If this return no issue then very sure unaligned transfer is what causing the issue.

[nirsap]

Hi Brian,
I’ll do the test again and provide detailed System-ILA debug info.
Can you please provide example of aligned transfer and zero padding?
The DMA itself should support unaligned transfers (Accord the settings).
I think that the RuntimeError is not with the unaligned transfer because it notifies for the starting address.
How can I control the starting address?
149 "DMA does not support unaligned transfers; "
150 "Starting address must be aligned to "
151 “{} bytes.”.format(self._align)
Thanks

[briansune]

@marioruiz

DMA API alignment support ground covers both alignment and unalignment?

[marioruiz]

@nirsap,

Can you please post the Python code your are using? If possible all of it.

Mario

[nirsap]

Attached.
Thanks,
ed_drivers.py (3.5 KB)
jupyer_notebook.ipynb (10.8 KB)

Nir

[nirsap]

Hi,
It seems that the problem is with the
The problem is with the flush but not the alignment.

RuntimeError Traceback (most recent call last)
Input In [12], in <cell line: 1>()
----> 1 drivers.send_data(dma_tx_send, input_buffer)
2 drivers.receive_data(dma_tx_receive, data_len)

File /home/xilinx/jupyter_notebooks/yhm_0x22113001_update/ed_drivers.py:55, in send_data(self, tx_buffer)
52 def send_data(self, tx_buffer):
53 # Trigger the DMA transfer and wait for the result
54 start_time = time.time()
—> 55 self.sendchannel.transfer(tx_buffer)
56 self.sendchannel.wait()
57 #self.register_map.MM2S_DMASR.IOC_Irq = 1

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/lib/dma.py:154, in _SDMAChannel.transfer(self, array, start, nbytes)
148 raise RuntimeError(
149 "DMA does not support unaligned transfers; "
150 "Starting address must be aligned to "
151 “{} bytes.”.format(self._align)
152 )
153 if self._flush_before:
→ 154 array.flush()
155 self.transferred = 0
156 self._mmio.write(
157 self._offset + 0x18, (array.physical_address + start) & 0xFFFFFFFF
158 )

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/buffer.py:107, in PynqBuffer.flush(self)
105 “”“Flush the underlying memory if necessary”“”
106 if not self.coherent:
→ 107 self.device.flush(self.bo, self.offset, self.virtual_address, self.nbytes)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/xrt_device.py:392, in XrtDevice.flush(self, bo, offset, ptr, size)
384 ret = xrt.xclSyncBO(
385 self.handle,
386 bo,
(…)
389 offset,
390 )
391 if ret >= 0x80000000:
→ 392 raise RuntimeError("Flush Failed: " + str(ret))

RuntimeError: Flush Failed: 4294967274

[marioruiz]

Hi @nirsap,

Can you elaborate on what would you like to accomplish?

Reading the code, it seems that you want to transfer element by element from the array. Having 32-bit elements in the array and the addressing being 64-bit it makes sense that you have aliment problems.

You typically want to use the DMA to transfer a large array to maximize performance. If you haven’t done it yet. I suggest you check out the DMA tutorial series here

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

Mario

[nirsap]

Hi @marioruiz ,
Thanks for the code review.
I’m using now the Python code just for debug and send short arrays.
My problem now is with the rx_buffer.freebuffer().
Do you think that the freebuffer() error is related to the alignment issue?

def receive_data(self, len):
rx_buffer = allocate(shape=(len, ), dtype=np.uint32)
self.recvchannel.transfer(rx_buffer)
self.recvchannel.wait()

# Free the buffer
rx_buffer.freebuffer()

[marioruiz]

can you try?

del rx_buffer