Hi,
I follow this design: GitHub - strath-sdr/rfsoc_qpsk: PYNQ example of using the RFSoC as a QPSK transceiver.
And I modify rf data converter ip the dac and adc sampling rate to 512MHz, and the interpolate factor and decimate factor to 8x
and I also removed some module in prior design
rfsoc_qpsk_bd.tcl (112.2 KB)
Thanks!