RuntimeError: DMA channel not idle

[alavala_suraj]

Hello,
I have had this error when I am trying to learn how to use transfer to and fro from DRAM via AXI-DMA. I am attaching my Jupyter notebook code and block diagram. I am using avnet ultra-96 v2 board. I have gone through the solution mentioned in

Run time error : DMA channel not idle

The error is telling you the DMA is not idle, so the transfer() can’t start. Do you get the error the first time you run this code, or do you get it after you run this code multiple times? I see you are at [76] cells that have been run. Can you share the whole notebook, details of the hardware design, and board you are using, PYNQ version and any other relevant details? Cathal

But could’ nt get it done.!

[marioruiz]

Hi,

I suggest you use an AXI4-Stream Data FIFO. The tlast signal of the mm2s channel is not being used and this can be causing an error.

You can use this tutorial as a guideline

Xilinx/PYNQ_Workshop/blob/master/Session_4/6_dma_tutorial.ipynb

Mario

[alavala_suraj]

Thanks Marioruiz,
I will try this solution and get back to you.

[alavala_suraj]

Hello Marioruiz,
I have corrected the mistake you have pointed out. I have created a tlast signal as shown in the diagram. After that, when I tried sending the data, My kernel ran for a long time but I couldn’t get any output. I have attached my modified block diagram.

[marioruiz]

I suggest you use an AXI4-Stream Data FIFO.
The DMA also uses the keep signal. And this is missing in your design.

[abdyoyo]

Where is the keep signal in the AXI4-Stream Data FIFO.

I could not find it in the disabled ports as well when I opened the DMA IP.

[briansune]

@abdyoyo

From what i understand keep is only used when unaligned transfer.
If aligned TRX no reason to use keep signal.

ENJOY~

[abdyoyo]

Thanks Brian.

The TRX is aligned as we are getting the data in frames perfectly.