When I tried to check the register mapping through the jupyter notebook, I got this error can someone help me to solve this?
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You need to post the rest of your code.
I don’t see your DMA in your ip_dict. Are you sure this is connected properly in your design?
I have some short video tutorials here:
This one may be of use:
Using the PYNQ 'register map' functionality
Cathal
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I shifted to the higher version of vivado(2022.2) and used the pynq v3.0.1 image.
Here I am able to access the DMA and could use the dma.register_map command to check the address.
I am getting a different address for the input buffer and source.
Why is it so?
As you replied in another post, I have initiated the output buffer with some non-zero values. When I received the output buffer, there was a overwrite for the first value alone and the rest of the values of the array was the same as initiated. Why it is happening like this?
I will attach my jupyter notebook file below.
Untitled.pdf (148.5 KB)
corresponding block design
project_newpd_dma.pdf (93.4 KB)
How did you create your IP (HLS, VHDL/Verilog etc.) and can you share this code?
Do you have a “TLAST” signal in the AXI stream output from your IP and if so, how do you set it?
I can see the receive DMA transfer is only 4 bytes long which would explain why you only see the first element of the output buffer written.
S2MM_LENGTH = Register(Length=4)
Cathal
… and please try to keep posts together - open a separate post for each new issue, and don’t add new issues to existing posts.
Cathal