When I tried to check the register mapping through the jupyter notebook, I got this error can someone help me to solve this? [image] [image]

You need to post the rest of your code. I don’t see your DMA in your ip_dict. Are you sure this is connected properly in your design? I have some short video tutorials here: This one may be of use: Using the PYNQ 'register map' functionality Cathal

Hi @cathalmccabe I shifted to the higher version of vivado(2022.2) and used the pynq v3.0.1 image. Here I am able to access the DMA and could use the dma.register_map command to check the address. I am getting a different address for the input buffer and source. Why is it so? As you replied in …

How did you create your IP (HLS, VHDL/Verilog etc.) and can you share this code? Do you have a “TLAST” signal in the AXI stream output from your IP and if so, how do you set it? I can see the receive DMA transfer is only 4 bytes long which would explain why you only see the first element of the ou…

… and please try to keep posts together - open a separate post for each new issue, and don’t add new issues to existing posts. Cathal

'DMA' object has no attribute 'register_map'

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'DMA' object has no attribute 'register_map'

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