Hello. Im trying to access a design maded in vivado on a Pynq-Z2 (img 2.6). This is the error that im getting whent accesing the ip.register_map
As yo can see, there is an error on ip.register_map.Memory_in_V.address. Why is that?
In an example that i found the instruction returns:
This is the my overlay info
Memory out_V has a size of 32 but Memory in_V is 256. Is this related to my data input size?
Dont understand why the address is not accessible.
Block design:
Resources:
HLS
N_IN = 128, N_OUT=10
Any ideas?
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After some investigation, i think that the issue may be that axi_lite bus is only 32bits (according to the axi reference guide pdf) while the input of my data is an array of 256bits so thats probably the issue So the input is an array of 256 data points, no 256bits.
I used m_axi now for the design but not sure how to complete the interface so i can access it later from pynq
And this is how i planned to write the data, is there a better way or something i need to change to use the m_axi? (these lines are for axi_lite)
Thanks
We haven’t implement support in register_map for types bigger than 64 bits hence your memory_in not showing up in your first design. you can use ip.read and ip.write to read and write the register directly by looking up the appropriate offset (512) in your case.
To use m_axi you need to use pynq.allocate to create buffers for your input and output and then write the physical_address property of the buffer to the register.
