Hi,
I am using Vivado 2018.1 and pynq v2.0 image.
I created the block design and uploaded the bitstream in Pynq jupyter notebook.
When I see the output I am getting all zeros as output. I created the block design for axi streaming interface.
Can you please help me to sort this issue?
I will attach the block design and my python code below.
project_newpd_dma.pdf (103.2 KB)
project_newpd.ipynb (7.0 KB)
This could be a problem with your IP, that it is writing out zeros.
Try initialize your output buffer with non-zero values, to check that when the output really is written out zeros.
Cathal
This doesn’t really give very much information.
This is a small snapshot of your simulation. Working in simulation != working in hardware.
Also, the test value in your notebook != your simulation value.
Did you try initialize the buffer with a non-zero value?
The DMA seems to complete properly. You can check the status register to verify there are no errors by printing the
dma.RegisterMap after your transaction has completed.
If you are confident your hardware is working, I would try add an ILA to the input and output of the IP, and also the inputs/outputs to the DMA. (I’d try this after the simple buffer initialize test).
Cathal
Cathal do you have any tutorial about AXIS simulation via Vivado AXI4-Stream Verification IP (Verilog + Sys-Verilog)?
If so then this could help @Arun_Kumar_Kurapati to reduce the compile and try iterations.
Enjoy~
What do you mean by initializing the buffer with a non-zero value?
I am very new to this can you please explain clearly?
And also should we check the register_map for IP or dma ?
Hi @cathalmccabe
I followed your suggestions and initiated the output buffer with non-zero values and when I print the output I am getting the first value as zero and the rest the values are the same as they were in the initiated buffer.
I do not understand why it is overwriting the first value as 0 and leaving the rest of the values as same.
I will attach my jupyter notebook file below, please help me to solve this issue.
project_newpd.ipynb (7.4 KB)
I have given the inputs as an array, is this the right way to pass the input to the DMA?
when I check the overlay information, it is not showing the DMA and it is showing only the hierarchy.
Why it is like that?
Below is the overlay information.
@Arun_Kumar_Kurapati
@cathalmccabe
Back to the inherent environment:
As @Arun_Kumar_Kurapati mentioned Vivado 2018.1 and pynq v2.0 image??
See → PYNQ SD Card image — Python productivity for Zynq (Pynq)
v2.0 is targeted 2016.1 not 2018.1
Please make sure environment is aligned with the targeted Vivado revision.
Although Xilinx had done a better job on cross revision support, the IP itself could have changes and compatibility might not 100% sure. When comes to software, it could even introduce uncertainties.
Enjoy~
Hi @briansune
Which version of the image should be used for vivado 2018.1
They haven’t mentioned about 2018.1 version.
@Arun_Kumar_Kurapati
@cathalmccabe
I have no good answer here it is not tested vs could works.
If logically speaking newer revision (big steps @ 2019 after) usually support old ones.
But your case is a newer tools is applied to older PYNQ version.
Meanwhile, as Cathal just mention the tlast shows doesn’t represent DMA is operating.
A: use the listed environment and revision pair
B: make sure DMA is familiar with simple example →
See example FIR DMA TRX →
C: sanity check HLS or custom IP
D:Join design
Enjoy~
Hi @briansune
sir, I didn’t understand what you mean, I have no clue how to proceed, can you please explain clearly?
I am also confused why from beginning, you got to use untested Vivado version on PYNQ.
It is clear mentioned that the Vivado and PYNQ revision pairs on the Readme document.
Unless you really know what you are doing, using aligned tools and image is highly recommended.
What you are telling us is that:
To conclude, start from basic and incrementally make your design.
Remember, the forum is to resolve PYNQ issues not helping engineer to build their designs.
This is a huge different!
Enjoy~
