Do overlays imply reconfiguration?

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Newby on pynq, bear with me…
As far as I know, overlays are a set of firmware plus software loaded dynamically on a booted (configured) Zynq SoC. does this mean when an overlay is loaded, the SoC is reconfigured?

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SOC could be referring to the whole system, so I’ll try avoid using this term to be clear.
In Xilinx terminology, Zynq has a Processing System or PS (this is teh ARM processor and hard peripherals/memory controllers, and Programmable logic PL (FPGA). You will see documentaton refer to PS and PL

The PS is initially configured at boot. E.g. clock configuration, memory controller, peripherals connected to PS. Some settings can be configured after boot if you know what you are doing - e.g clock settings, other settings wouldn’t make sense to change. E.g. don’t change your memory controller settings or you will like crash your system!

When an overlay is loaded, it programs the PL. The “firmware” or software to interact with the design in the PL can be run.

Cathal

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Thanks, I wanted to avoid the term ‘FPGA’ as some may understand only the PL. Xilinx call the Zynq family SoC/ MPSoC, that’s why I use it for what is in the chip, nothing else.
What I understand then, is that an overlay reconfigures and replaces the previous one.
A bit strange… why having the first one then?

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Some applications may only have one overlay. Some may switch multiple times depending on the function required at any given time. You could have multiple design on your board, and program whichever one you want at any given time.

PYNQ is also a development framework, so having run time programmable capability from the board is a great feature.

Cathal

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5

Thanks, I have been wondering how this works too. I am new to PYNQ as well. This is running on the Petalinux OS right? Is the OS is “suspended” while PL is reconfigured? Is there some type of teardown process to remove devices from previous overlay? Where could I find more information about this? The Xilinx flow I am familiar with is to configure PS and load PL in FSBL before higher level SW/Linux. I am not sure how to handle dynamic linux device configuration compared to simple flow w/ device tree generated from HDF.