Hello
I was working with FPGA, ARM, Zynq previously in the pure Verilog/C, but I know that I don’t know everything about Zynq. I recently got an Pynq Z2 board. How does exactly dynamic Overlay load works? I mean, how it works without whole system restart while you are loading configuration to the whole SoC (ARM & FPGA)? Does it just pause system, reload everything, and the whole system works from the context stored in RAM (and CPU registers maybe also)? I tried to connect via SSH, and during Overlay reload it responds. So it seems to not restart the system. Which paper can I read more about this? For the future needs I am interested how to reload the FPGA+ARM configuration from the pure Linux software.
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First welcome =]
For this question there are system PS and PL.
=> processing system (PS ) and a Programmable Logic (PL) unit
Once you see the title you should immediate know why. The HARDCORE is a fixed silicon aka ARM CPU runs any time and cannot be reconfigured like LUT. So the processor can handle easily on the FPGA manager aka PL either partial reconfiguration or full reconfiguration.
Same concept applies on partial reconfiguration as you claims you have experiences on FPGA. PR is what a part of system kept fixed and relied on the fixed system to reconfigure the dynamic ones.
Google or Chat GPT is what you need.
ENJOY~
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okay, but in project Vivado I am adding Zynq block, where I can config peripherials that affects CPU part too (DRAM parameters etc.)
so as I understand correctly it doesn’t touch the running ARM processor?
I had more experience with pure FPGA, less with Zynq Soc
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Double click the block to configure like IP blocks.
Unclear question
Nope this is same as PCIe or Ethernet to partial reconfigure the PL, just the host is now a no chip host rather than PC.
ENJOY~
I am just wondering how it works when you config in Vivado Zynq Processing part, where you could affect also the CPU part in some way (for example change the DRAM config). But maybe it changes the DRAM controller settings and everything is transparent to the ARM CPU.
Have you had any MCU or CPU background? If not this is why you are asking such questions.
The question you propose is how settings in the Vivado are loaded to the actual hardware.
Then same question, how the netlist of the HDL is given to the FPGA?
Same idea applies.
ENJOY~
Hello please be a little more patient
I did software for STM32s as well as other MCUs (bare metal without Cube) but I was accustomed that reprogram is always related to the system reset. At least for these architectures.
Zynq is programmable logic plus ARM CPU. I understand that PL is separated from ARM. So overlays reload only PL.
This is what I understand
However some SoC settings (within Overlay) could affect CPU part (as far I understand for this moment, I am not very deep into Zynq).
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Welcome to the PYNQ forums.
Zynq is programmable logic plus ARM CPU. I understand that PL is separated from ARM. So overlays reload only PL.
This is what I understand
However some SoC settings (within Overlay) could affect CPU part (as far I understand for this moment, I am not very deep into Zynq).
The PS is always running. Overlay() configures the PL and can update some PS settings.
Explanation:
Boot configuration
The PYNQ image is used to boot the Processing System (PS). This configures the ARM processor, and things like the clocks and memory controller - so this is like a default configuration.
Later, when you load overlays, most of the PS remains untouched by PYNQ. For example, if you create a new Vivado project with different DDR settings, PYNQ will ignore these. These settings are only applied at boot and should not change, so it would not make sense to use different settings.
Runtime configuration settings
There are other settings like the PS - PL clocks that can change at runtime.
The PYNQ Overlay class will read the clock settings from the Overlay design files and update the clocks at runtime (just before the bitstream is downloaded to configure the PL)
AXI bus isolation
Depending on your PL design, you may be able to just overwrite a new configuration. However, if you had a design that is continuously read/writing on any of the AXI buses, if the PL reconfiguration happens in the middle of an AXI transaction the whole board will hang. For example, if you are doing video processing and using the DDR memory for a framebuffer, a reconfig has a good chance of hanging the board. You can use DFX AXI shutdown registers or other logic to protect against this. You will see this in some of the example PYNQ overlay designs. (Look near the HP port form Zynq 7000 designs)
Cathal
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Dear Cathal
This is exactly what I needed
Thank you very much 
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