Error with axis and input buffers

Good afternoon, excuse me, I am currently working on an IP for a digital signature algorithm. This algorithm is implemented in Vitis HLS, which performs simulation, synthesis, and co-simulation correctly. The top function is as follows with its pragmas. I don’t know if someone can guide me because it is in an infinite loop when I run it on my notebook. It could be a problem with the chosen axes or that I am not assigning them correctly in the notebook.
I am working pynq z2.

test_falcon_vrfy(const char hexpk[1795], const char nonce[81], const char mensaje[3000],
		 int len_msg, const char firma[2051], int *salida)

#pragma HLS INTERFACE s_axilite port=return bundle=CTRL

#pragma HLS INTERFACE m_axi port=hexpk bundle=DATA
#pragma HLS INTERFACE m_axi port=nonce bundle=DATA
#pragma HLS INTERFACE m_axi port=mensaje bundle=DATA
#pragma HLS INTERFACE m_axi port=firma bundle=DATA

#pragma HLS INTERFACE s_axilite port=len_msg bundle=CTRL
#pragma HLS INTERFACE s_axilite port=salida bundle=CTRL

unsigned char pk[3000];
size_t pklen;
size_t u;
falcon_vrfy fv;

pklen = hextobin(pk, sizeof pk, hexpk); //pasar la llave publica

if (!falcon_vrfy_set_public_key(&fv, pk, pklen)) {

	unsigned char r[40], sig[3000];

	size_t rlen, siglen, msglen, v;
	int z;

	rlen = hextobin(r, sizeof r, nonce);

	siglen = hextobin(sig, sizeof sig, firma);

	falcon_vrfy_start(&fv, r, rlen);
	falcon_vrfy_update(&fv, mensaje, msglen);
	z = falcon_vrfy_verify(&fv, sig, siglen);
	if (z <= 0) {
	}else {

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Hi @Salo_Moreno,

The port m_axi_DATA is not connected in your block design.


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