Failed to find axi_dma_0 and custom HLS IP core in Tysom board PYNQ

[harivan]

I am using Vivado 2022.1 and Tysom board ZU7EV.

I write here below HLS IP code in cpp.

I also attach the tcl script to create the block diagram in IP integrator. I also attach here the block diagram.

I also attach the .hwh files.

In PYNQ code, when I query for print(ol.ip_dict.keys()) where ol is the overlay object, then it shows only zynq processor and does not show axi dma, custom IP core or anyother IP core like smart connect.

I could not attach .bit file which is 19.3 MB too large for forum limit of 10 MB.

Kindly help me resolve this issue.

Thank you,

harivan

design_1.hwh (270.7 KB)

renew_tcl.tcl (5.4 KB)

HLS IP cpp code:

#include <hls_stream.h>
#include <ap_axi_sdata.h>

typedef ap_axiu<32,0,0,0> pkt;

void stream_pass_through(hls::stream& in, hls::stream& out) {
#pragma HLS INTERFACE axis port=in
#pragma HLS INTERFACE axis port=out
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
//#pragma HLS INTERFACE ap_ctrl_none port=return

pkt data;

LOOP: while (!in.empty()) {
    #pragma HLS PIPELINE II=1
    data = in.read();
    data.data += 1;
    out.write(data);
}

}

[marioruiz]

Hi @harivan,

Welcome to the PYNQ community.

It would appear that you have not assigned addresses to these IP, please check the Address Editor tab and assign the addresses and re-generate the bitstream.

Mario

[harivan]

@marioruiz

Welcome to the PYNQ community.

It would appear that you have not assigned addresses to these IP, please check the Address Editor tab and assign the addresses and re-generate the bitstream.

Hi @marioruiz ,

Thanks for your reply. I had not set the DDR4 RAM to a preset yesterday apart from not assigning the addresses in the address editor.Thank you for correcting me.

Now after making these changes, my pynq code is detecting zynq ps, axi dma, hls ip core, but it does not show other IPs like smart connect etc. Is this expected.

And the dma gets stuck before giving response output from HLS IP.

What could be the error.

Please look at the attachments.

Thanks,

harivan

renew_tcl.tcl (7.8 KB)

design_1.hwh (368.3 KB)

[harivan]

Hi @marioruiz ,

In the attached MMIO is found missing, what is the fix , kindly help.

[marioruiz]

@harivan

Now after making these changes, my pynq code is detecting zynq ps, axi dma, hls ip core, but it does not show other IPs like smart connect etc. Is this expected.

Yes, this is correct. These IP cores are not memory mapped.

And the dma gets stuck before giving response output from HLS IP.

I wrote an extensible debugging blog about this. Please check it

Debugging Common DMA Issues [Part 3]

Debugging Common DMA Issues If you frequent the PYNQ forum, one of the most common questions/issues we get is why DMA transfer do not work. In part 3 of this series, I will reproduce these issues and use both the register_map and ILA to identify and address these issues. DMA channel not started Often, we see users reporting something like this. --------------------------------------------------------------------------- RuntimeError Traceback (most recent call last) Input In [4], in <cell line:…

In the attached MMIO is found missing, what is the fix , kindly help.

This is related to the DMA issue

Your original issue is resolved. I would suggest you create another topic for the DMA issue, only if the debugging blog is not enough.