It looks like your IP doesn’t have an AXI Slave interface and therefore it won’t be in the Zynq PS memory map and PYNQ won’t auto discover it.
You have an AXI Master on your IP connected to the HP port, so your IP maps the PS DRAM into its memory space.
It looks like the ap_control interface should be an AXI slave interface.
CHeck the documentation for the INTERFACE pragma in HLS.
You may want to add this, but you should check the documentation and make sure you understand what this is doing before you add it:
#pragma HLS INTERFACE s_axilite port = return
This may be helpful:
https://xilinx.github.io/Vitis-Tutorials/2020-1/docs/my-first-program/cpp_kernel.html
Cathal
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