I have an ADC that I’d like to sample at least a 1kHz signal with, but the standard I2C speed of 100kHz limits me to ~3kBaud which gives me pretty unreliable data for a 1kHz signal. At lower rates of around 500Hz the data is fairly reliable (albeit, I see some spurious noise that I think I can filter out…).
I would like to over sample my signal so I was wondering if anyone has had any luck increasing the I2C clock on the Pynq MicroBlaze to 400kHz (and beyond). And if so, is the process to simply modify the base overlay IIC module in Vivado? What about the MicroBlaze, does it need to be tweaked as well?
Perhaps it is obvious and I will discover the answer myself as I dig through the project, but I wanted to get community input before I got too far.
First if your ADC can support high-speed mode can even turn up to 3.4Mb/s depends on your module/IC.
For fast speed mode it is just general i2c protocol. Google about the setup of HSM
The communication is a bit different at the beginning of the I2C protocol
So if this is not inherently supported by the AXI-I2C then you had to write your own AXI+ AXI_stream design via HLS or Verilog/ VHDL.
Meantime, always pay attention to your pull-up resistor as I had experience a client event put a 1Meg pull-up on I2C.
Thanks @briansune for your prompt response. And good point on pull-ups – the module I have has some options and supports fast and HS modes. I see in the datasheet (for the ADC081C) where it talks about the special command for HS mode; so I think I’m squared away for how to put the ADC into HSM (yes, I agree that I would probably need to write my own or use an opensource I2C module to utilize HSM). I think I can get by with fast mode for my use case for now, so I just need to go through the process of changing the clock speed of the base overlay I2C module – this is where my question comes in. That being, I’m wondering if anyone has completed this task and, if so, which module(s) do I need to update.
Chris I guess this is a community ask and answer place rather than business place for hiring and commit. Maybe there are even nicer people here would do it free.
But I will highly suggest before asking / pay people, why not Google a bit more as you might not even notice there are exist example from vendor or even others repositories.
Yes, you are mistaken . I’m a bit confused by your responses… I’m not looking to hire anyone, I’m looking for community support (this is the PYNQ support forum). I am querying the community to see if someone has already performed this task on the PYNQ-Z1 and, if so, what parameters in the base overlay IIC module (and/or MB) they changed to achieve 400kHz SCL rate.
FWIW, Google has left me without answers, which is why I am here.
Please, if you have performed this task already, do share which parameters you had to change (if you remember). If not, I will wait patiently for others to chime in and start working on solving the problem on my own (if no one responds).
Well
From the line “I’m wondering if anyone has completed this task and, if so, which module(s) do I need to update.”
As I2C Bus Master Control looks need to buy license so I had confused you are trying to buy others work here. My bad, but you need to wait others that had used these modules before and also used the similar FPGA before. I had not work out those module before sadly.
Meantime, I do double check I didn’t wrongly read anything: https://docs.xilinx.com/v/u/1.02a-English/axi_iic_ds756
Fast Speed Mode =/= High Speed Mode as setup protocol is a bit different what I experience.
But I come up to an idea that you could try:
Start HSM setup @ 400KHz
wo restart nor stop change the clock rate to 1MHz
Send the Address and the data package accordingly on software control
This could work as well.
For hardware control I don’t think it is supported.
. I’m a bit confused by your responses… I’m not looking to hire anyone, I’m looking for community support (this is the PYNQ support forum). I am querying the community to see if someone has already performed this task on the PYNQ-Z1 and, if so, what parameters in the base overlay IIC module (and/or MB) they changed to achieve 400kHz SCL rate.