Use PYNQ to realize deep learning on zcu104, customize the IP core of convolution, and PL calls the data in DDR for convolution operation. When PYNQ-Z2 is used, it is configured automatically and directly. In addition, AXI HP0 transfers data from DDR. After replacing the zcu104 with the same configuration, the results are all 0. What’s wrong with my configuration? Attach the wiring diagram of PYNQ-Z2 and ZCU104
The following is ZCU104. In addition, a warning appears after automatic connection: [BD 41-1629]</zynq_ ultra_ ps_ e_ 0/SAXIGP2/HP0_ LPS_ OCM>is excluded from all addressable primary spaces.
If I want to add OCM access permissions, how do I map OCM to the address space of the PL master node? No relevant settings are seen in the zynq UltraScale processor
Hi sq0515,
I hope you are doing well! I can’t see from the outset what is wrong with your configuration but that just might be due to my lack of experience with deep learning implementations (so if anyone else is reading this with more expertise please chime in!).
That said I hope I can help you with this specific question.
The OCM is accessed by other system elements using its 128-bit AXI slave port, if you expand the ports zynq_ultra_ps_e_0 Block we can confirm if this is set up correctly or not. Please share a screenshot!
I have a few more questions that may help us figure this out! What kind of results are you expecting at the output? what frequency was the previous design on the Pynq-z2 running at? and what frequency is your design on the Zcu104 running at?
