How to design circuits at the level of LUTs and connectivity?

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I have a Pynq Z1. This question may be generic to all Xilinx FPGAs but I know so little that I don’t know whether or not I need a Z1-specific answer.

I want to be able build circuits in Verilog or VHDL, specifying them at the level of LUTs and the connections between them. I have only a Pynq Z1 available to me. What might be a curriculum that will get me to that goal? What references, books, open source code, online tutorials, etc.?

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Some material here:

You may want to try this first:

Cathal

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