[Edit: Spilt post]
Re: Tutorial: Creating a new Verilog Module Overlay - #3
Thankyou for sharing,
I encountered a problem while making the design work
- i am using vivado 2022.1 in ubuntu
- i was trying for pynq zu board, it said the io resources exceeds your board so i dismissed lalst two functions called bitwisexor/xnor it worked for me i synthesized the design
- made an IP calling the module and added the module to the sources of the new ip synthesized the ip saved it everything is done top notch
- while doing final step i made a block design imported the ip added the module IP is Instantiating and tried synthesizing the wrapper but giving me errors like
Your question is about a Verilog design/Vivado project. You would be better posting this question on the Xilinx forums.
Error 2 is telling you that your design has more IO (input output or just “pins”) than are available on the board/device you picked.
Error 4 is telling you that you have not given any IOSTANDARD (the electrical standard for the pin) nor LOC (location - which pin you want to use) constraints for 92 IO in your design. i.e. You have not assigned the ports/pins in your design to physical pins on the Zynq device you are using.
You can go back and open the synthesized project and open the IO planning view to see the IO in your design, and in the same view you can graphically assign pins.
For reference, the IO constraints for the PYNQ-ZU board are here: https://xilinx.github.io/PYNQ-ZU/pynqzu_master.xdc
You can also enter constraints using this text file. The port names in your design have to match the ports in the XDC file.
Thankyou for your reply sir
gonna try this