I created the block design for my verilog design by adding my IP to it and generated the bitstream successfully. Before generating bitstream it didn’t ask me to give voltages or pins so is this correct or Im going wrong? and when I go to i/o planning I was not able to see my actual inputs and outputs in it.
Can someone please help me.
And also,
How to create overlays in PYNQ for our verilog design. I mean how to write a python code in jupyter for our verilog design to implement in PYNQ Z1 board?
What have you connected your i/o to? If they are only connected back to the PS, then you will have no external pins that need IO constraints. Think of these as internal connections inside the chip.
If you don’t provide constraints, you should see errors when you try to build the bitstream.
I mean how to write a python code in jupyter for our verilog design to implement in PYNQ Z1 board?
You can find some tutorials here:
You can find a short playlist of tutorial videos here:
If you can provide more detail about what you are trying to do, and where you are stuck, it would help.
