Hello, I’m Hi, I’m working on adaptive clock signals for FPGA.
We are currently developing using PYNQ-Z1 board, and I wonder how to input clock signals from outside.
Also, when an adaptive clock signal is entered, is there a module or Python code that can see power consumption detection or power efficiency inside the PYNQ?
Hello Chung,
I will answer the second part I expect myself had more experience and could give this more deeply.
FPGA power consumption is just an estimation when Vivado report.
While considering in real-life the most commonly way is to measure the current consumption at the source aka after the DC Jack or the 12V power line as DC-DC power-loss I will considered as part of the system consumption.
So if there are no shunt nor hall-effect current sensor and voltage rail probing to compute the I-V the result can only be estimated on Python about general Flop switching and LE consumption, clock-tree converge etc.
In the pass I had suggested add the hall-effect current sensor at the high-side like IC:
to FPGA design.
Which communicated via SPI and good understand on the overall power consumption of the system or FPGA itself.