Hi,
If you mark a reply as solution, please open a new post for future questions. The second question is not related to the first one, hence it will not help other people.
There are detailed tutorials on the use of DMA and DMA + HLS IP. I suggest you have a look, these should answer your questions.
PYNQ DMA tutorial (Part 1: Hardware design)
This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …
Tutorial: using a HLS stream IP with DMA tutorial (Part 1: HLS design)
In a previous tutorial I showed how to use the AXI DMA to stream data between memory to AXI stream interfaces. The DMA tutorial used an AXI stream FIFO to do a loopback test to show how to use the DMA. This tutorial will show how to create and add a HLS IP with an AXI input stream, and AXI output stream. This tutorial will be split into two parts. This part 1 shows how to build the HLS IP, part 2 shows how to build the Vivad…
Mario
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