Operate on 2D-Array

[alienflip]

Hey again all

I am using PYNQ-Z2 v2.7, with Vivado/Vitis 2022.1.

Currently trying to do something on a 2d array - the pseudo code would be:

for(int ix = 0; ix < size; ix++){
    for(int iy = 0; iy < size; iy++){
        if(ix + iy % 2 == 0){
            OUTPUT[ix][iy] = INPUT[iy][ix];
        }
        else{
            OUTPUT[ix][iy] = 0;
        }
    }
}

Ideally, the notebook would look like this:

import time, random, numpy
from pynq import Overlay, allocate
import pynq.lib.dma

ol = Overlay('./design_1.bit')
ol.download()

dma0 = ol.axi_dma_0
dma1 = ol.axi_dma_1

arr = numpy.random.randint(10, size=(128,128))
zeros = numpy.zeros(arr.shape, dtype=int)

in_buffer = allocate(shape=arr.shape, dtype=numpy.int32) 
out = allocate(shape=zeros.shape, dtype=numpy.int32) 

numpy.copyto(in_buffer, arr)
numpy.copyto(out, zeros)

t_start = time.time()
dma0.sendchannel.transfer(in_buffer)
dma0.recvchannel.transfer(out)
dma0.sendchannel.wait()
dma0.recvchannel.wait()
t_stop = time.time()

in_buffer.close()
out.close()

print("Hardware execution speed: ", t_stop - t_start)
print("Array out: ", out)

I am just wondering how to go about reading the buffer here from hls? How would we go about dereferencing particular elements?

I noticed this post mentions HLS ARRAY_PARTITION and HLS PIPELINE … is there some inbuilt hls FPGA functionality here already for array handling?

Could someone help demystify the pragmas?!

I also looked at the vitis examples, but they dont reference hls:stream … maybe the idea is to combine the approaches?

… anyhow …

Thanks!

[marioruiz]

Hi @alienflip,

This is not really a PYNQ question. However, there are many posts with similar questions.

Please check out these tutorials

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

Tutorial: AXI Master interfaces with HLS IP

PYNQ HLS AXI Master tutorial Introduction Previous tutorials show how to build IP with AXI stream interfaces and how they can be connected in a Vivado project to an AXI DMA. The DMA can be controlled from PYNQ to send data to the IP and receive results. AXI stream interfaces are useful if you are connecting multiple IP together in a dataflow type architecture. However, you don’t have to use AXI streams and DMAs with HLS IP. HLS supports AXI master interfaces which can read and write data as r…

Mario

[alienflip]

Ah, ok … where best to ask questions about the pragmas?

[marioruiz]

In the Xilinx forums https://support.xilinx.com/s/topic/0TO2E000000YKXtWAO/hls?language=en_US

[alienflip]

Can follow here