After some experimentation and reading through some guides about DMA on the Zynq 7020 board
(e.g. Element14 or This Forum) and experimenting with memory access I have the following situation:
I’m using a PYNQ-Z2 Board with no further modifications to the image and my own overlay that I created in Vivado. For the application that the FPGA will be used in later, any use of the PS should be avoided if possible for reliability reasons. For debugging, some AXI interfaces still exist to probe the overlay with Jupyter Notebook. But after testing, everything should be hardware-triggered.
I experimented with an old Altera FPGA Board of mine which uses RAM LPM Blocks to communicate with the external RAM-IC by enabling reading and writing using provided data and addresses.
My question is finally:
What is the most straightforward way to interface directly from PL (using vhdl or HLS IPs) with RAM without the use of the PS?
I tried interfacing with the AXI-interface of the DMA IP or setting up MiG Series 7, however, I’m stuck using configuring the AXI4 Master for the DMA or the pins for the MiG. Are there “PL-only” tutorials that I can follow or did I miss something in the ones that I listed?
I hope this is not a duplicate and that I followed all the rules on the forum, as I just created this account
Thank you!
PS: The data I want to write is a 128bit Stream that updates at 4kHz and I want to record for a couple of seconds. Later on this entire data block shall be read-out and sent to a tbd sdr transmitter.
Hi,
If you are using a PYNQ-Z2 I presume you want to use the PS DRAM. You don’t need MIG, the memory controller is in the PS. You can access the PS DRAM fromo the AXI HP port.
You mentioned you don’t want to use the PS at all during running. From the PS, you will need to allocate some DRAM for your IP initially.
For the application that the FPGA will be used in later, any use of the PS should be avoided if possible for reliability reasons
You are using the PS RAM, but you don’t need the processor to do anything which I think is OK for your use case.
You can find some tutorials I made here:
This one may be useful, using a HLS AXI Master:
You can connect the AXI master to the HP port to access PS RAM.
You can also use a DMA (see other tutorials), and you can also do similar with HDL.
You are using the PS RAM, but you don’t need the processor to do anything which I think is OK for your use case.
Okay, I guess I didn’t specify my request clearly enough. As you said, it should be fine as long as I don’t need to interface the Linux/Jupyter Interface
I might come back for some questions here if that is fine. If I can get it to work, I’ll mark your reply as the solution
Okay so I took a look at your tutorial about the AXI Master interfaces and if I understand you correctly, the assignment of the memory to store the data is done through Jupyter. Unfortunately, that will not be possible in the final deployment of the Board.
What is should be used for is as a data gathering system aboard a university CubeSat and the actual OBC of the satellite will send commands (probably via SPI) to the FPGA to collect sensor data (some Mbs in total) and then also send the data via an also FPGA-based SDR on the same chip. We will not be using a PYNQ Board in the final application but rather such a board and currently we are prototyping with the PYNQ Board.
So am I correct in assuming memory allocation is not really possible from PL?
Memory is controlled by the PS. When the bootable image is created, it (usually!) assigns all of the DRAM to the OS.
PL is like any other software application in relation to accessing DRAM. It needs memory space allocated before it can use it so that it doesn’t interfere with the OS. You can dynamically allocate memory at runtime as shown in tutorials (pynq allocate).
Alternatively, you could build a custom image for your board and only assign/allocate some of the physical memory to the OS. The remaining memory can’t/won’t be used by the OS, but you could access it directly from the PL.
This is a bit like hard coding the memory address for the PL IP. Would this work for you?
Can you provide me with some information on building a custom image for memory access from PL? I can only find information online regarding building custom images for different hardware and not for allocating memory away from the PS.
