PYNQ: PYTHON PRODUCTIVITY

How to use the official axilite IP created by HLS tool

Hello, I made a axilite IP from the official on offical example which is a adder of two or three numbers. (c += a + b)
I made no change just change part to a pynq board.
Then I use vivado block design to autoconnect the axilite IP we mde and zynq processer IP.
With .bit, .tcl, .hwh files import to a pynq board.
We haven’t get the result we want. the result is always zero.chrome_QdG8PN55qK

I also have another small question, I think it is because we just need to tpye offset address on pynq’s notebook.
Like this, address 0x4300010 is real address, and in note book 0x0010 is okey.

eclipse_w5uaRgWnNP

it is 0x43c00010, I revise it.

Did you add the hls pragma “#pragma HLS INTERFACE ap_ctrl_none port=return” ?
If you didn’t, you need to start your IP by writing 0x01 to your IP’s 0x00 address.
You can also read your IP’s status by reading this address.
// AXILiteS
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved

1 Like

yeap it work ,it is so nice .
thank you so much,chrome_erYQrQlEa9