Hello, I made a axilite IP from the official on offical example which is a adder of two or three numbers. (c += a + b)
I made no change just change part to a pynq board.
Then I use vivado block design to autoconnect the axilite IP we mde and zynq processer IP.
With .bit, .tcl, .hwh files import to a pynq board.
We haven’t get the result we want. the result is always zero.
I also have another small question, I think it is because we just need to tpye offset address on pynq’s notebook.
Like this, address 0x4300010 is real address, and in note book 0x0010 is okey.