Hello,
I’v written an AXI Stream IP core in verilog and successfully used it in verilog. Before getting to my question I would like to thank the pynq staff for the amazing platform they created.
So let’s get to my problem. I’m trying to convert that AXI Stream code mentioned above to an AXI Lite IP Core. Before that I wrote a simple AXI Lite adder in verilog and connected it to the zynq PS (Block Design Picture is attached). when i try to access it’s registers with “add_ip.register_map” I get the following error : “AttributeError: register_map only available if the .hwh is provided”
after searchin in the PYNQ support topic I found this link :
I found out that I have to specify my registers in the vivado IP packager’s “addressing and memory” tab.
is there any manual on how to do that?
when i click add register it just want’s a name for the register. what other parts should I fill and how should I address my registers and memory?
After you enter the name (and press OK) a new sub-table will appear in which you can enter other properties of the register.
You also need to upload the hwh file along with the bitstream to the PYNQ device, These need to be in the same folder and have the same name except for the .bit and .hwh extensions.
The .hwh file can be found by exporting the hardware (File>Export>Export_Hardware) from the project that the block diagram you posted is in, after it is implemented. The hardware files are in a zip archive but with a different extension, .xsa if you are using Vivado 2019.x.
Dear ggillett,
thank you for your response.
I have done the things you said so far. I just don’t know how to enter the properties of the registers. for example the base address of the address blocks and the address offset of the registers.
I have two 32 bit registers for my adder (adds two 16 bit nIumber in the first register and puts the output in the second register).
I’ve uploaded all three .bit, .tcl and the .hwh file into my PYNQ overlay folder.
It is about your address decoding matching the register offsets used… You could try setting the register offsets to 0 and 1, not sure if you used the AXI lite peripheral flow in the packager. I’ve never used that my self.
Thank you for your response.
I asked this question in the xilinx Forum and found out this configuration is correct. 32 bit registers needs 4Byte for addressing so in my verilog code I need to check the address[3:2] for address decoding. so this is my config so far.
Now when i write data to my first register (slv_reg0) via add_ip.register_map.slv_reg0 the second register also get’s this value and I don’t get the result of the adder in the second register.
any thoughts on this?
Adding named registers only makes the design easier to use in PYNQ. It doesn’t change the way your hardware works.
I’m guessing your Verilog is wrong. Did you simulate it?
I’m assuming you are you writing this from scratch yourself. I would suggest you use the AXI IP Wizard from the Vivado IP packager to create and AXI template. Simulate this and understand how it works, and then modify it for your design.
I used the AXI IP Wizard in vivado to generate my code. I attached the verilog files below. I checked the files and found nothing wrong. I’d appreciate it if you could take a look at them also.
