I’v written an AXI Stream IP core in verilog and successfully used it in verilog. Before getting to my question I would like to thank the pynq staff for the amazing platform they created.
So let’s get to my problem. I’m trying to convert that AXI Stream code mentioned above to an AXI Lite IP Core. Before that I wrote a simple AXI Lite adder in verilog and connected it to the zynq PS (Block Design Picture is attached). when i try to access it’s registers with “add_ip.register_map” I get the following error : "AttributeError: register_map only available if the .hwh is provided"
after searchin in the PYNQ support topic I found this link :
I found out that I have to specify my registers in the vivado IP packager’s “addressing and memory” tab.
is there any manual on how to do that?
when i click add register it just want’s a name for the register. what other parts should I fill and how should I address my registers and memory?
Thank You in advance.