The AXI interface is the default interface type used in Vivado. One way to do this would be to add an AXI interface to your design. An AXI stream for your pixels would be the most straightforward. You can then stream data to your IP using a DMA.
You could also build an AXI master interface where your IP could access DRAM directly (without needing a DMA). This interface is more complicated though.
For any of the AXI interfaces, I would recommend you use a Wizard in Vivado to generate the HDL for the AXI interface(s) you want. I posted in another topic about this recently:
Once you generate the template, you can integrate your Verilog into the generated code.
Cathal