I’m not sure about standard testbenches, but the testbenches are usually easier to write.
You didn’t ask this, but it may help; I’d never write my own AXI interface logic as I think you did in this example.
You can generate a HDL (VHDL/Verilog) AXI interface template in Vivado, and add your HDL for the logic. I’d always use this if I needed a HDL AXI interface.
Create and Package IP wizard
If you use HLS, it will generate the AXI interfaces automatically.
There are AXI protocol checkers you can add to your design in Vivado too if you want.
Cathal