I am trying to implement PYNQ Overlay for RFSoC4x2 board using PYNQ-Overlay for ZCU111 board as reference.
I have built Vivado project for 4x2 board and generated Bitstream file successfully. Now when I am trying to run the Python code (CMAC_Intro.ipynb) somehow my Jupyter Server gets disconnected and UART connection breakes, specifically when I run the code snippet below
I am using SD image provided by PYNQ for 4x2 board. I am not sure about the SD image to be used nor any code to be changed. I am very new to this topic so if in-case I missed out any reference or document please point out. If anyone have a solution please share, I highly appreciate that.
I have divided code into 2 cells then to this issue still appears, the issue is occurring while binding the drivers flashing the overlay bitstream is successfully done. I have checked using,
ol?
which gives me this output
Type: Overlay
String form: <pynq.overlay.Overlay object at 0xffff9c6c5a50>
File: /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py
Docstring:
Default documentation for overlay design_1_wrapper.bit. The following
attributes are available on this overlay:
IP Blocks
----------
axi_dma_1 : pynq.lib.dma.DMA
axi_intc_0 : pynq.overlay.DefaultIP
cmac_usplus_0 : pynq.lib.cmac.CMAC
zynq_ultra_ps_e_0 : pynq.overlay.DefaultIP
Hierarchies
-----------
None
Interrupts
----------
None
GPIO Outputs
------------
None
Memories
------------
PSDDR : Memory
Class docstring:
This class keeps track of a single bitstream's state and contents.
The overlay class holds the state of the bitstream and enables run-time
protection of bindings.
Our definition of overlay is: "post-bitstream configurable design".
Hence, this class must expose configurability through content discovery
and runtime protection.
The overlay class exposes the IP and hierarchies as attributes in the
overlay. If no other drivers are available the `DefaultIP` is constructed
for IP cores at top level and `DefaultHierarchy` for any hierarchies that
contain addressable IP. Custom drivers can be bound to IP and hierarchies
by subclassing `DefaultIP` and `DefaultHierarchy`. See the help entries
for those class for more details.
This class stores four dictionaries: IP, GPIO, interrupt controller
and interrupt pin dictionaries.
Each entry of the IP dictionary is a mapping:
'name' -> {phys_addr, addr_range, type, config, state}, where
name (str) is the key of the entry.
phys_addr (int) is the physical address of the IP.
addr_range (int) is the address range of the IP.
type (str) is the type of the IP.
config (dict) is a dictionary of the configuration parameters.
state (str) is the state information about the IP.
Each entry of the GPIO dictionary is a mapping:
'name' -> {pin, state}, where
name (str) is the key of the entry.
pin (int) is the user index of the GPIO, starting from 0.
state (str) is the state information about the GPIO.
Each entry in the interrupt controller dictionary is a mapping:
'name' -> {parent, index}, where
name (str) is the name of the interrupt controller.
parent (str) is the name of the parent controller or '' if attached
directly to the PS.
index (int) is the index of the interrupt attached to.
Each entry in the interrupt pin dictionary is a mapping:
'name' -> {controller, index}, where
name (str) is the name of the pin.
controller (str) is the name of the interrupt controller.
index (int) is the line index.
Attributes
----------
bitfile_name : str
The absolute path of the bitstream.
dtbo : str
The absolute path of the dtbo file for the full bitstream.
ip_dict : dict
All the addressable IPs from PS. Key is the name of the IP; value is
a dictionary mapping the physical address, address range, IP type,
parameters, registers, and the state associated with that IP:
{str: {'phys_addr' : int, 'addr_range' : int, 'type' : str, 'parameters' : dict, 'registers': dict, 'state' : str}}.
gpio_dict : dict
All the GPIO pins controlled by PS. Key is the name of the GPIO pin;
value is a dictionary mapping user index (starting from 0),
and the state associated with that GPIO pin:
{str: {'index' : int, 'state' : str}}.
interrupt_controllers : dict
All AXI interrupt controllers in the system attached to
a PS interrupt line. Key is the name of the controller;
value is a dictionary mapping parent interrupt controller and the
line index of this interrupt:
{str: {'parent': str, 'index' : int}}.
The PS is the root of the hierarchy and is unnamed.
interrupt_pins : dict
All pins in the design attached to an interrupt controller.
Key is the name of the pin; value is a dictionary
mapping the interrupt controller and the line index used:
{str: {'controller' : str, 'index' : int}}.
pr_dict : dict
Dictionary mapping from the name of the partial-reconfigurable
hierarchical blocks to the loaded partial bitstreams:
{str: {'loaded': str, 'dtbo': str}}.
device : pynq.Device
The device that the overlay is loaded on
Init docstring:
Return a new Overlay object.
An overlay instantiates a bitstream object as a member initially.
Parameters
----------
bitfile_name : str
The bitstream name or absolute path as a string.
dtbo : str
The dtbo file name or absolute path as a string.
download : bool
Whether the overlay should be downloaded.
ignore_version : bool
Indicate whether or not to ignore the driver versions.
device : pynq.Device
Device on which to load the Overlay. Defaults to
pynq.Device.active_device
gen_cache: bool
if true generates a pickeled cache of the metadata
Note
----
This class requires a HWH file to be next to bitstream file
with same name (e.g. `base.bit` and `base.hwh`).
I have checked what you said, Yes Jupyter Kernel is shutting down repeatedly and No message is displayed.
If base overlay already have CMAC how could I test ? I am using ZCU111 Overlay as a Reference. Is there any reference you could provide and can you expand your thoughts please. Sorry if my question is too basic I am very new to this.
Thank you for your help you got me out of the trouble. I was wondering is there any other resources that I could use to check whether the data transfer is at 100Gps.
