Intefarcing of custom IP having HLS stream of ap_uint

Support
1

Hello I am trying to implement convolution through finn hlss library. I am facing issues while creating the interface for Vivado. I can not connect it to DMA.

My top function looks like this:
#include “edgedetection.h”
#include <hls_stream.h>
using namespace hls;
#include “convlayer.h”

#define IFC IFM_Channels1
#define OFC OFM_Channels1

typedef stream<ap_uint<IFC * INPUT_PRECISION>> dataInS;
typedef stream<ap_uint<OFC * ACTIVATION_PRECISION>> dataOutS;

void ConvLayer_B_custom(dataInS &in, dataOutS &out, int const numReps) {
#pragma HLS INTERFACE s_axilite port=return bundle=control
#pragma HLS INTERFACE s_axilite port=numReps bundle=control
#pragma HLS INTERFACE axis port=&in bundle=hostmem
#pragma HLS INTERFACE axis port=&out bundle=hostmem
#pragma HLS DATAFLOW
static FixedPointWeights<SIMD,ap_uint<32>,PE,TILES> weights= {
-1,-2,-1,
0, 0, 0,
1, 2, 1
};

ConvLayer_Batch<K, IFC, IFD, OFC, OFD, SIMD, PE, Slice<ap_int<INPUT_PRECISION> >, Slice<ap_int >, Identity>(
in, out, weights, PassThroughActivation<ap_int>(), numReps, ap_resource_dsp());

}

My vivado block design looks like this:

image
image1115×624 56.5 KB

I can not connect my input and output port to DMA.

2

Hi @Sheikh_Talha,

Welcome to the PYNQ community.

Why are you bundling both AXI4-Stream interfaces to the same name? Each of the should have their own name.

Mario

3

Even when I make those changes like this:

typedef stream<ap_uint<IFC * INPUT_PRECISION>> dataInS;
typedef stream<ap_uint<OFC * ACTIVATION_PRECISION>> dataOutS;

void ConvLayer_B_custom(dataInS &in, dataOutS &out, int const numReps) {
#pragma HLS INTERFACE s_axilite port=return bundle=control
#pragma HLS INTERFACE s_axilite port=numReps bundle=control
#pragma HLS INTERFACE axis port=&in bundle=in_hostmem
#pragma HLS INTERFACE axis port=&out bundle=out_hostmem
#pragma HLS DATAFLOW

static FixedPointWeights<SIMD,ap_uint<32>,PE,TILES> weights= {
-1,-2,-1,
0, 0, 0,
1, 2, 1
};

ConvLayer_Batch<K, IFC, IFD, OFC, OFD, SIMD, PE, Slice<ap_int<INPUT_PRECISION> >, Slice<ap_int >, Identity>(
in, out, weights, PassThroughActivation<ap_int>(), numReps, ap_resource_dsp());

}

I am still getting the same type of ports when i import my ip to vivado block design.

4

You shouldn’t be using &in and &out in the directives. The pragma for the AXI4-Stream interfaces should be

#pragma HLS INTERFACE axis port=in bundle=in_hostmem
#pragma HLS INTERFACE axis port=out bundle=out_hostmem

If after this change, you are still facing issues. I suggest you ask the question in the FINN or Xilinx forums.

Mario