I’m encountering an issue with IP visibility in Jupyter Notebook. I’ve developed a basic IP for RGB to grayscale conversion using Vivado (VHDL), but I’m unable to locate it in Jupyter Notebook.
The error message I receive is “Could not find IP or hierarchy rgb2gray in overlay”.
Additionally, when I create this IP in Vivado HLS, it appears and functions correctly in Jupyter Notebook.
If anyone can offer insights or suggestions to help resolve this issue, I would greatly appreciate it. Thank you!
Does the (VHDL) IP have an AXI interface and a register map?
Are you using a block design, and did you provide the HWH? This is where PYNQ reads info about IP in the design.
If you are not using the Block Design in Vivado, if you have a register map on your IP, you can hardcode MMIO addresses. This isn’t ideal, but may work for you?
Yes, I am indeed using a block design in Vivado, and I have provided the HWH file. Additionally, the VHDL IP I’ve developed does have an AXI interface and a register map. I made sure to adhere to the AXI protocol standards during its implementation.
Despite these efforts, I’m still encountering the issue where the IP doesn’t appear in Jupyter Notebook. The error message persists: “Could not find IP or hierarchy rgb2gray in overlay”.
Any further insights or suggestions would be greatly appreciated.
I’ve tried accessing the ip_dict to retrieve a list of IPs, but unfortunately, the IP I’m looking for isn’t listed there. I’ve also double-checked for any possible naming discrepancies, but the name matches exactly.
I’ll gather the requested materials – a screenshot of the block design and a copy of the HWH file – and share them with you shortly.
Your rgb2gray2 IP only has AXI stream interfaces. It does not have a AXI slave interface, which means it doesn’t have a register map with control and status registers you can read or write. This is why it doesn’t show in the IP dict.
If you want to control or check status of this IP, you need to modify it to add control registers or signals.
I was wondering if you might know of any tutorials or resources that provide guidance on adding control registers or signals to FPGA IPs,
particularly within the context of PYNQ development.
Once again, thank you for your assistance in identifying the root cause of the problem.
There isn’t anything special you do for hardware design for PYNQ.
For Zynq design, you would usually use an AXI slave interface to control an IP. You may be better searching for “Zynq” tutorials on FPGA forums or webpages.
