It is so strange that pynq can't transfer value correct with a axilite IP

Hi, I design a IP with HLS tools, it should transfer value 223, I have valided it on HLS simulation,but it is always “91”.
On HLS, it is 223 with the sim
But on pynq,It become 91
It is so strange.
Here is HLS design:
Snipaste_2021-02-22_12-53-24 Snipaste_2021-02-22_12-50-46
Here is vivado design:

Hi @AllenChenChao,

What is in offset 0x28?


have you see the function axi4_sampen()? and have you see the parameter of int& Sampen, its offset would be 0x28.

you could see it in vivado address or sdk registers.

Yes I saw the function prototype. But, I do not have the code nor the Vivado project, that is why I asked.

This seems not to be related to pynq itself but rather to the IP you designed. Perhaps asking in the Xilinx forums will be more useful to get an answer

Yeap, Thank you for your suggestion^_^

noticing parameter int& SampEn in function axi4_sampen.
SampEn could be used directly on the C/C++ code.
I think I 'd better improve my C/C++ code ability.
I try again, and it is right now. It is so strange, but it is okey. The problem hasn’t been ensured.

You most likely will get the same result if your write the host code in C/C++.

Is SampEn a constant value?


nope, it the value read by PS with python.
It is the index result we need for such algorithm. :blush:

I have one question. It is float yes?
If you are parsing float to integer in python to send it to axi register.
Python will read it as integer and will need to parse it one more time from integer to float :slight_smile:

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You are right, integer is more easy for FPGA^_^