Transfer float from PS to PL using AXI DMA

[Th_ng_Nguy_n_D_c]

-PYNQ Version 3.0.1
-Board: Ultra 96
-Vivado & VITIS HLS 2022.0.2

I am trying to transfer float from PS to PL via AXI DMA. This is my block design in Vivado:

Basically the IP core only increments input by 5. The HP0 port on PS is set to 64 bits. This is the config for axi dma:

This is my hls code for my IP core:

I managed to get correct results when I used ap_axis<32,2,5,6> as data type for stream interface. However, the results are all dummy numbers if I use hls::axis<float, 0, 0, 0> as some people suggested.

May I know any ideas how to fix this?

[Riya_Sachdeva]

Float transfers are very painful Vitis 2022.1 onwards for some reason. I am yet to pinpoint the exact issue, but I found some solutions online and implemented them, here: GitHub - riyasach189/Vitis_HLS_2022.1_Examples: This is a collection of some examples designed in the Vivado Design Suite.