I face this problem for a while at this point. I made a custom IP using Vitis HLS and when i try to write value at any address, the kernel dies. The module is connected to the zynq using an AXI interconnect. Other IPs connected to it have no problem writing values at specific addresses, only my IP.
flitru.cpp (1.7 KB)
This is the HLS code but i tested different codes and still doesn’t seem to work.
hI @Filip_Ion,
This is the same code as the colorconvert from PYNQ. PYNQ/boards/ip/hls/color_convert/color_convert.cpp at master · Xilinx/PYNQ · GitHub
Have you assigned the address base address correctly to the IP?
Mario
Hi. Yes i have assigned an address. When i run
" overlay? " command in jupyter it shows the module.
And yes it is the color convert code from pynq and i tried different codes but the kernel still dies when i try to use .write function to my module.
Any suggestions ? Thanks.
please provide a Python code snippet of what you’re trying to run.
Default documentation for overlay filtru.bit. The following
attributes are available on this overlay:
video/top_0 : pynq.overlay.DefaultIP → this is the module i made in vitis HLS
video/hdmi_in/frontend/axi_gpio_hdmiin : pynq.lib.axigpio.AxiGPIO
video/hdmi_out/frontend/hdmi_out_hpd_video : pynq.lib.axigpio.AxiGPIO
system_interrupts : pynq.overlay.DefaultIP
video/axi_vdma : pynq.lib.video.dma.AxiVDMA
video/axis_switch_0 : pynq.overlay.DefaultIP
video/hdmi_out/frontend/axi_dynclk : pynq.overlay.DefaultIP
video/hdmi_out/frontend/vtc_out : pynq.overlay.DefaultIP
video/hdmi_in/frontend/vtc_in : pynq.overlay.DefaultIP
video/hdmi_in/pixel_pack : pynq.lib.video.pipeline.PixelPacker
video/hdmi_in/color_convert : pynq.lib.video.pipeline.ColorConverter
video/hdmi_out/color_convert : pynq.lib.video.pipeline.ColorConverter
video/hdmi_out/pixel_unpack : pynq.lib.video.pipeline.PixelPacker
ps7_0 : pynq.overlay.DefaultIP
Hi @Filip_Ion,
You are not writing to the filtru_1 IP. You are grabbing a handle of a hierarchy base.video.top_0.
Or there’s a mismatch between your first screenshot with the IP and what is on the FPGA.
filtru_1 should appear in the base.ip_dict for you to be able to use it.
My fault. there is a mismatch between the photos, its the same module but renamed. filtru_1 is now named top_0
Please, make sure the reset and clock are connected properly.
They are connected correctly, I moved the s_axi_control signal to other axi interconnect because the bus was busy (i don’t know with what process) and now i can write data. Thanks for the patience.
