KV 260 MIPI/Composable pipeline python syntax error

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1

PYNQ Version: 3.01
Board: KV260 Vision AI starter kit
Tools: Vivado 2020.2(composable)
Hello, I am trying to use a Raspberry Pi camera with the KV260 board. I have a video pipeline working already(atleast with DMA and AXI stream). I googled around and found that the Composable video pipeline has a MIPI capture pipeline and thought I could reuse that for my project.

However I run into some issues trying to build the project. Initally it could not find the board files, so i cloned the Xilinx board store into the path and renamed the folders so that it would find it. It for some reason still gives me errors for this, but now it continues until it fails at a syntax error.

The log is shown below(I edited out some BOARD[49-26] warnings since it gives this for all parts which is a lot). I am using vivado 2020.2 to build as specified, and running ‘make’ in the KV260 folder. I assume the pynq version shouldn’t matter when just trying to build?

make -C ../Pynq-ZU/ip/vitis_vision/ DEVICE=zynq-us -j4
make[1]: Entering directory '/bitsim/work/anwa-x/kria_ref/PYNQ_Composable_Pipeline/boards/Pynq-ZU/ip/vitis_vision'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/bitsim/work/anwa-x/kria_ref/PYNQ_Composable_Pipeline/boards/Pynq-ZU/ip/vitis_vision'
make -C ../ip/boards/ZCU104/base/ hls_ip
make[1]: Entering directory '/bitsim/work/anwa-x/kria_ref/PYNQ_Composable_Pipeline/boards/ip/boards/ZCU104/base'
vivado -mode batch -source build_ip.tcl -notrace

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source build_ip.tcl -notrace
Skipping building color_convert_2
Checking color_convert_2
Skipping building pixel_pack_2
Checking pixel_pack_2
Skipping building pixel_unpack_2
Checking pixel_unpack_2
HLS IP builds complete
INFO: [Common 17-206] Exiting Vivado at Thu Mar 21 17:20:34 2024...
make[1]: Leaving directory '/bitsim/work/anwa-x/kria_ref/PYNQ_Composable_Pipeline/boards/ip/boards/ZCU104/base'
vivado -mode batch -source cv_dfx_4_pr.tcl -notrace

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source cv_dfx_4_pr.tcl -notrace

WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /home/anwa-x/.Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts *:kv260:* -latest_file_version'.
get_board_parts: Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2427.148 ; gain = 2.016 ; free physical = 7336 ; free virtual = 15280

ERROR: [BD::TCL 103-2041]  board file is not found. Please install the board file either manually or using the Xilinx Board Store
INFO: [Common 17-206] Exiting Vivado at Thu Mar 21 17:21:06 2024...
cp default_paths.json overlay/cv_dfx_4_pr_paths.json
make -C dts/
make[1]: Entering directory '/bitsim/work/anwa-x/kria_ref/PYNQ_Composable_Pipeline/boards/KV260/dts'
dtc -I dts -O dtb -o mipi.dtbo mipi.dtsi
mipi.dtsi:71.5-40: Warning (reg_format): /fragment@2/__overlay__/i2c@80030000:reg: property has invalid length (16 bytes) (#address-cells == 2, #size-cells == 1)
mipi.dtbo: Warning (pci_device_reg): Failed prerequisite 'reg_format'
mipi.dtbo: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
mipi.dtbo: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
mipi.dtbo: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
mipi.dtbo: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
mipi.dtsi:62.26-103.6: Warning (avoid_default_addr_size): /fragment@2/__overlay__/i2c@80030000: Relying on default #address-cells value
mipi.dtsi:62.26-103.6: Warning (avoid_default_addr_size): /fragment@2/__overlay__/i2c@80030000: Relying on default #size-cells value
mipi.dtbo: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
mipi.dtbo: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
make[1]: Leaving directory '/bitsim/work/anwa-x/kria_ref/PYNQ_Composable_Pipeline/boards/KV260/dts'
cp dts/mipi.dtbo overlay/cv_dfx_4_pr.dtbo
python3 ../../pynq_composable/parser.py --hwh overlay/cv_dfx_4_pr.hwh
  File "../../pynq_composable/parser.py", line 81
    if 'xilinx.com:ip:xlslice' in (vlnv := m.get('VLNV')):
                                        ^
SyntaxError: invalid syntax
Makefile:46: recipe for target 'dict' failed
make: *** [dict] Error 1
2

Hi @dewasser,

Welcome to the PYNQ community.

First, I suggest you use the branch v1.1.0-dev so it aligns with Vivado 2022.1 and PYNQ 3.0.1.

File “…/…/pynq_composable/parser.py”, line 81
if ‘xilinx.com:ip:xlslice’ in (vlnv := m.get(‘VLNV’)):
^
SyntaxError: invalid syntax

You can ignore this error as it only relates to generated a cached version of the metadata, this will be generated on target anyways. Otherwise, you need a Python version 3.8 or newer.

Mario

3

Thanks. Unfortunately I don’t have Vivado 2022.1 only 2022.2

Do you know how I can open the project in normal vivado mode instead of batch as make does? It would be helpful since the part I really need is the MIPI capture pipeline. I can’t open it because of the board file errors

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4

An .xpr file should be generated, and you can open this.

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