Hi Folks,
pynq doesn’t seem to be properly interpreting the address map of my overlay even though I’ve provided it bd and hwh files.
My design is from a block design (A) in Project A.
This design uses a User IP block I created and exported as a user IP from a block design in Project B
When I instantiate the overlay I find that tab completion is broken and the address space in the IP dict doesn’t reflect that I’d set.
Tab completion on the overlay, ol
, object proffers “ol.gen3_reschan_0” and “ol.gen3_reschan_0//S_AXI_CTRL”, the latter of whihc is not valid python. I think the latter should be ol.gen3_reschan_0.S_AXI_CTRL.
ol.hierarchy_dict[‘gen3_reschan_0’] shows
{‘device’: <pynq.pl_server.device.XlnkDevice at 0x7f67029a20>,
‘driver’: ,
‘fullpath’: ‘gen3_reschan_0’,
‘gpio’: {},
‘hierarchies’: {},
‘interrupts’: {},
‘ip’: {‘S_AXI_CTRL’: {‘addr_range’: 16384,
‘device’: <pynq.pl_server.device.XlnkDevice at 0x7f67029a20>,
‘driver’: pynq.overlay.DefaultIP,
‘fullpath’: ‘gen3_reschan_0/S_AXI_CTRL’,
‘gpio’: {},
‘interrupts’: {},
‘mem_id’: ‘S_AXI_CTRL’,
‘parameters’: {‘C_BASEADDR’: ‘0xA0034000’,
‘C_HIGHADDR’: ‘0xA0037FFF’,
‘Component_Name’: ‘test_channelizers_gen3_reschan_0_1’,
‘EDK_IPTYPE’: ‘PERIPHERAL’},
‘phys_addr’: 2684567552,
‘registers’: {‘Memory_phase0_V’: {‘access’: ‘read-write’,
‘address_offset’: 8192,
‘description’: ‘Memory phase0_V’,
‘fields’: {},
‘size’: 4096},
‘Memory_resmap_V’: {‘access’: ‘read-write’,
‘address_offset’: 4096,
‘description’: ‘Memory resmap_V’,
‘fields’: {},
‘size’: 4096},
‘Memory_toneinc_V’: {‘access’: ‘read-write’,
‘address_offset’: 4096,
‘description’: ‘Memory toneinc_V’,
‘fields’: {},
‘size’: 4096},
‘align_V’: {‘access’: ‘read-only’,
‘address_offset’: 8192,
‘description’: ‘Data signal of align_V’,
‘fields’: {‘RESERVED’: {‘access’: ‘read-only’,
‘bit_offset’: 9,
‘bit_width’: 23,
‘description’: ‘Data signal of align_V’},
‘align_V’: {‘access’: ‘read-only’,
‘bit_offset’: 0,
‘bit_width’: 9,
‘description’: ‘Data signal of align_V’}},
‘size’: 32}},
‘state’: None,
‘type’: ‘MazinLab:mkidgen3:gen3_reschan:1.12’}},
‘memories’: {}}
I would have expected the following addresses based on what I set in A’s address map and the offsets in the HLS block generated driver .h files.
Memory_resmap_V: 0xA0020000 + 0x1000 (From the bin_to_res_0 HLS block)
align_V: 0xA0020000 + 0x2000 (From the bin_to_res_0 HLS block)
Memory_phase0_V: 0xA0034000 + 0x1000 (From the resonator_dds_0 HLS block)
Memory_toneinc_V: 0xA0034000 + 0x2000 (From the resonator_dds_0 HLS block)
I’ve tried using mmio.read/write on 0xA0020000+0x1000 and I just get an invalid address space error.