This is the main vhdl code that is generated.
Generated by MATLAB 9.5 and HDL Coder 3.13
β
β Rate and Clocking Details
β Model base rate: -1
β Target subsystem base rate: -1
β
β Module: untitled_ip
β Source Path: untitled_ip
β Hierarchy Level: 0
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY untitled_ip IS
PORT( IPCORE_CLK : IN std_logic; β ufix1
IPCORE_RESETN : IN std_logic; β ufix1
AXI4_Lite_ACLK : IN std_logic; β ufix1
AXI4_Lite_ARESETN : IN std_logic; β ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); β ufix16
AXI4_Lite_AWVALID : IN std_logic; β ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); β ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); β ufix4
AXI4_Lite_WVALID : IN std_logic; β ufix1
AXI4_Lite_BREADY : IN std_logic; β ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); β ufix16
AXI4_Lite_ARVALID : IN std_logic; β ufix1
AXI4_Lite_RREADY : IN std_logic; β ufix1
AXI4_Lite_AWREADY : OUT std_logic; β ufix1
AXI4_Lite_WREADY : OUT std_logic; β ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); β ufix2
AXI4_Lite_BVALID : OUT std_logic; β ufix1
AXI4_Lite_ARREADY : OUT std_logic; β ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); β ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); β ufix2
AXI4_Lite_RVALID : OUT std_logic β ufix1
);
END untitled_ip;
ARCHITECTURE rtl OF untitled_ip IS
β Component Declarations
COMPONENT untitled_ip_dut
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); β ufix16_En15
In2 : IN std_logic_vector(15 DOWNTO 0); β ufix16_En15
Out1 : OUT std_logic_vector(15 DOWNTO 0) β ufix16_En14
);
END COMPONENT;
COMPONENT untitled_ip_axi_lite
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; β ufix1
AXI4_Lite_ARESETN : IN std_logic; β ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); β ufix16
AXI4_Lite_AWVALID : IN std_logic; β ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); β ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); β ufix4
AXI4_Lite_WVALID : IN std_logic; β ufix1
AXI4_Lite_BREADY : IN std_logic; β ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); β ufix16
AXI4_Lite_ARVALID : IN std_logic; β ufix1
AXI4_Lite_RREADY : IN std_logic; β ufix1
read_ip_timestamp : IN std_logic_vector(31 DOWNTO 0); β ufix32
read_Out1 : IN std_logic_vector(15 DOWNTO 0); β ufix16_En14
AXI4_Lite_AWREADY : OUT std_logic; β ufix1
AXI4_Lite_WREADY : OUT std_logic; β ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); β ufix2
AXI4_Lite_BVALID : OUT std_logic; β ufix1
AXI4_Lite_ARREADY : OUT std_logic; β ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); β ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); β ufix2
AXI4_Lite_RVALID : OUT std_logic; β ufix1
write_In1 : OUT std_logic_vector(15 DOWNTO 0); β ufix16_En15
write_In2 : OUT std_logic_vector(15 DOWNTO 0); β ufix16_En15
reset_internal : OUT std_logic β ufix1
);
END COMPONENT;
β Component Configuration Statements
FOR ALL : untitled_ip_dut
USE ENTITY work.untitled_ip_dut(rtl);
FOR ALL : untitled_ip_axi_lite
USE ENTITY work.untitled_ip_axi_lite(rtl);
β Signals
SIGNAL reset : std_logic;
SIGNAL ip_timestamp : unsigned(31 DOWNTO 0); β ufix32
SIGNAL reset_cm : std_logic; β ufix1
SIGNAL reset_internal : std_logic; β ufix1
SIGNAL write_In1 : std_logic_vector(15 DOWNTO 0); β ufix16
SIGNAL write_In2 : std_logic_vector(15 DOWNTO 0); β ufix16
SIGNAL Out1_sig : std_logic_vector(15 DOWNTO 0); β ufix16
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); β ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); β ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); β ufix2
BEGIN
u_untitled_ip_dut_inst : untitled_ip_dut
PORT MAP( In1 => write_In1, β ufix16_En15
In2 => write_In2, β ufix16_En15
Out1 => Out1_sig β ufix16_En14
);
u_untitled_ip_axi_lite_inst : untitled_ip_axi_lite
PORT MAP( reset => reset,
AXI4_Lite_ACLK => AXI4_Lite_ACLK, β ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, β ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, β ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, β ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, β ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, β ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, β ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, β ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, β ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, β ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, β ufix1
read_ip_timestamp => std_logic_vector(ip_timestamp), β ufix32
read_Out1 => Out1_sig, β ufix16_En14
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, β ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, β ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, β ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, β ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, β ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, β ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, β ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, β ufix1
write_In1 => write_In1, β ufix16_En15
write_In2 => write_In2, β ufix16_En15
reset_internal => reset_internal β ufix1
);
ip_timestamp <= to_unsigned(2103081659, 32);
reset_cm <= NOT IPCORE_RESETN;
reset <= reset_cm OR reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
END rtl;
The folder below contains the entire folder of the generated ip core. When i add the ip core to vivado, i selected this folder.
untitled_ip_v1_0.zip (190.0 KB)