Multiple Clocks in C++?

Are there any plans within Xilinx to support multiple clocks in C/C++ HLS designs?

UG902 says this:

For C and C++ designs only a single clock is supported. The same clock is applied to all functions in the design.

I need to implement a clock module that provides pass-through, divided, gated clocks, and which is part of a larger design. These clocks need to feed lower-level components. This singular requirement is pushing the entire project to be done in Verilog.

It would be really helpful to be able to do low-level RTL work in C++, but I constantly find myself having to straddle HLS and RTL to get meaningful work done. This limitation with the clock is just one example where something that is common in HDLs which is made difficult in C++ HLS.

I understand that this be possible with SystemC, but I have much better tooling available for C++ development, including unit test frameworks, test coverage tools, and formal verification tools. There just isn’t the breadth of tools available for SystemC that there is for C++.

Any feedback on this would be greatly appreciated.

You would be better trying to post this on the Xilinx forum