Changing clock frequency using C

[Pranav_Chaitanya]

Hey everyone,
[Using: PYNQ Z1]
I am trying to change the clock frequency of the PL clock (Clocks.fclk0_mhz = 50 in python) using C. I guess we can write the frequency onto the memory address associated with the PL clock. I am using Vitis_hls and Vivado 2020.2.

it would be of great help if any of you could tell me where to look for that address so that I can perform a DMA and write the frequency into it. I can also look int vitis_hls or vivado if someone could tell me where the info related to clock address would be.

[cathalmccabe]

The is the PYNQ forum. If you want to use Zynq with C you may be better posting on the Xilinx forums.
You can find register info in the Zynq TRM.
https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Register-slcr-FPGA0_CLK_CTRL

Cathal

[Pranav_Chaitanya]

Thank you soo much.

[Pranav_Chaitanya]

#include <fcntl.h>
#include <stdio.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <unistd.h>
#include <string.h>
#include <math.h>

int main() {
int fd = open(“/dev/mem”, O_RDWR | O_SYNC);
if (fd < 0) {
perror(“Failed to open /dev/mem”);
return -1;
}

void *map = mmap(NULL, 0x10000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0xF8000000);

if (map == MAP_FAILED) {
    perror("Failed to mmap");
    return -1;
}

// relavant bits
#define srcsel      0x30
#define divisor0    0x3F00
#define divisor1    0x3F00000


#define srcsel_val    0x0 
#define divisor0_val  0xA  // First cascade divider value
#define divisor1_val  0x1  // Second cascade divider value

volatile int* clk_ctrl = (volatile int*)(map + 0x170); 

// clear 
*clk_ctrl &= ~srcsel;
*clk_ctrl &= ~divisor0;
*clk_ctrl &= ~divisor1;

//set
*clk_ctrl |= (srcsel_val << 4);
*clk_ctrl |= (divisor0_val << 8);
*clk_ctrl |= (divisor1_val << 20);

}

I could control the clock using this code.