I have just received the RFSoC4x2 and I am trying to test the MTS example from RFSoC-MTS Repo and I just can not figure it out why I can not synchronize between tiles 226 and 224.
I am conducting a test with an external sinus wave signal from VSG60A, however, this is what I get.
Important to mention is, PLL1 and PLL2 are not locked. and I am trying to figure out why. I mean they are supposed to be locked. why they are not.
I would be glad about some insights and directions, I guess it starts with LMK04828.
Thank you for your time.
I have figured out that allegedly no MTS occurred.
I did not get why to negate block 0 (ADC0) at tile 224. I also negated block1 (ADC1) but it seems to be out of phase in the same tile (tile 224).
Nathan I’ve seen you merged it to the main branch @najachim @njachimi
maybe also you guys @cathalmccabe or @marioruiz know more what’s behind that.
I highly appreciate a little bit of information on that.
Thanks a lot!
If you check the RFSoC 4x2 Schematic you will see that the N/P pins for ADC 224 were connected incorrectly during board design which is why they need to be corrected.
The issue becomes apparent in MTS use.
It is detailed and insightful!