Hi,
In a previous project, the PYNQ-Z1(v2.4) image works well with my AXI slave hardware accelerator. Now I’m porting to ZCU-104. The Python driver is leveraged from what it worked in PYNQ-Z1. However, it occurred the following error on both v2.4 and v2.5 on ZCU-104 while executing the Python driver.
/usr/local/lib/python3.6/dist-packages/pynq/overlay.py:299: UserWarning: Users will not get PARAMETERS / REGISTERS information through TCL files. HWH file is recommended.
warnings.warn(message, UserWarning)
INFO: FPGA bitstream loading time: 0.5471346378326416
Traceback (most recent call last):
File “mlp_float_test_adv_0217.py”, line 80, in
mlp_ip = overlay.mlp_core
File “/usr/local/lib/python3.6/dist-packages/pynq/overlay.py”, line 327, in getattr
return getattr(self._ip_map, key)
File “/usr/local/lib/python3.6/dist-packages/pynq/overlay.py”, line 601, in getattr
"Could not find IP or hierarchy {} in overlay".format(key))
AttributeError: Could not find IP or hierarchy mlp_core in overlay
—Code snippet------
from pynq import Overlay
end = time.time()
print("INFO: FPGA overlay class loading time: ",end-start,‘\n’)
start = time.time()
overlay = Overlay(ol_path)
end = time.time()
print("INFO: FPGA bitstream loading time: ",end-start,‘\n’)
mlp_ip = overlay.mlp_core
However, after some debug attempts, I came up with the following solution that resolved the issue. My question is how to explain the issue. Appreciate for any comments. Thank you
--------------After revised, it worked…
from pynq import Overlay
from pynq import MMIO
end = time.time()
print("INFO: FPGA overlay class loading time: ",end-start,‘\n’)
start = time.time()
overlay = Overlay(ol_path)
overlay.download()
end = time.time()
print("INFO: FPGA bitstream loading time: ",end-start,‘\n’)
mlp_ip = MMIO(0xA0000000,0x4000)
#mlp_ip = overlay.mlp_core